Imaging apparatus

ABSTRACT

An imaging apparatus includes a plurality of pixels, a signal holding unit, first and second control electrodes. Each of the plurality of pixels includes a photoelectric conversion unit, and an amplification element to amplify signals based on signal charges generated by the photoelectric conversion unit, in which the plurality of pixels output signals for performing a phase contrast detection type of focal point detection. The signal holding unit is in an electrical pathway between an output node of the photoelectric conversion unit and an input node of the amplification element, in which signals for performing the phase contrast detection type of focal point detection are held. The first control electrode is configured to transfer a signal of the photoelectric conversion unit to the signal holding unit. The second control electrode is configured to transfer a signal for performing the phase difference detection type of focal point detection.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a Continuation of U.S. application Ser. No.13/764,657, filed Feb. 11, 2013, which claims the benefit of JapanesePatent Application No. 2012-033367 filed Feb. 17, 2012, which are herebyincorporated by reference herein in their entireties.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an imaging apparatus, and particularlyrelates to an imaging apparatus that performs a phase contrast detectiontype of focal point detection at the imaging face.

2. Description of the Related Art

With the related art, configurations performing a phase contrastdetection type of focal point detection at an imaging face of an imagingapparatus are known. Japanese Patent Laid-Open No. 2010-288083, forexample, discloses a CMOS imaging device that includes imaging pixels togenerate image generation signals, and focal point detection pixels togenerate phase contrast detection signals. Also, for frames in whichfocal point detection is performed, all imaging pixels of the imagingdevices are exposed simultaneously, and the imaging signal generated asa result of this exposure is read out. For frames in which focal pointdetection is not performed, the imaging signals from the imaging devicesare read out by a slit rolling read out. Further, FIG. 4 and paragraph0018 of Japanese Patent Laid-Open No. 2010-288083 describe a collectiveelectron shutter being performed to align accumulated point-in-time ofall pixels.

However, despite that the configuration in Japanese Patent Laid-Open No.2010-288083 does not perform the phase contrast detection type of focalpoint detection at the imaging face, but does perform the collectiveelectronic shutter, enough consideration has not been given to theconfiguration of pixels to actually achieve these results. ReferencingFIGS. 2 and 4 of Japanese Patent Laid-Open No. 2010-288083 illustratesthat a charge generated at a photoelectric conversion unit istransferred together for all pixels to a floating diffusion (hereafter,FD). Also, this charge is accumulated in the FD until a timing for theread out of each row of pixels. The configuration of the FD is basicallynot suitable for long-term holding of charges. Specifically, it isdifficult to create a configuration in which little dark current isgenerated during the signal holding period. Further, it is alsodifficult to remove noise signals related to the pixel signals. It istheoretically possible to remove noise by including several rows worthof circuits to hold noise signals in a column circuit, but the spacetaken by the column circuits may become large. Further, the length ofthe holding period for the noise signal column circuit differs for eachrow, which may decrease the precision of noise removal.

SUMMARY OF THE INVENTION

It has been found desirable to provide an imaging apparatus that iscapable of a phase contrast detection type of focal point detection atthe imaging face, with a configuration that is capable of performing aglobal electronic shutter with low noise.

According to one aspect, an imaging apparatus includes: a plurality ofpixels each including a photoelectric conversion unit, and anamplification element to amplify signals based on signal chargesgenerated by the photoelectric conversion unit, in which the pluralityof pixels output signals for performing a phase contrast detection typeof focal point detection; and a signal holding unit in an electricalpathway between an output node of the photoelectric conversion unit andan input node of the amplification element, in which signals forperforming the phase contrast detection type of focal point detectionare held.

Further features of the present invention will become apparent from thefollowing description of exemplary embodiments with reference to theattached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top view of an imaging region of an imaging apparatus in afirst Example of a first Embodiment.

FIG. 2 is an enlarged top view of the imaging region of the imagingapparatus in the first Example of the first Embodiment.

FIG. 3 is an equivalent circuit diagram illustrating a first pixel ofthe imaging apparatus in the first Example of the first Embodiment.

FIG. 4A is a cross-sectional diagram illustrating the first pixel of theimaging apparatus in the first Example of the first Embodiment, and FIG.4B is a diagram illustrating the potential of the parts illustrated inFIG. 4A.

FIG. 5 is a total block diagram illustrating the imaging apparatus inthe first Example of the first Embodiment.

FIG. 6 is a diagram illustrating control pulses corresponding to theimaging region of the imaging apparatus in the first Example of thefirst Embodiment.

FIG. 7A is a cross-sectional diagram illustrating the first pixel of theimaging apparatus in a second Example of the first Embodiment, and FIG.7B is a diagram illustrating the potential of the parts illustrated inFIG. 7A.

FIG. 8 is a diagram illustrating control pulses corresponding to theimaging region of the imaging apparatus in the second Example of thefirst Embodiment.

FIG. 9 is a top view of the imaging region of the imaging apparatus in afirst Example of a second Embodiment.

FIG. 10 is an expanded top view of the imaging region of the imagingapparatus in the first Example of the second Embodiment.

FIG. 11 is an equivalent circuit diagram illustrating the first pixel ofthe imaging region of the imaging apparatus in the first Example of thesecond Embodiment.

FIG. 12A is a cross-sectional diagram illustrating the first pixel ofthe imaging apparatus in the first Example of the second Embodiment, andFIG. 12B is a diagram illustrating the potential of the partsillustrated in FIG. 12A.

FIG. 13 is a total block diagram illustrating the imaging apparatus inthe first Example of the second Embodiment.

FIG. 14 is a diagram illustrating control pulses corresponding to theimaging region of the imaging apparatus in the first Example of thesecond Embodiment.

FIG. 15 is a diagram illustrating the potential of the imaging region ofthe imaging apparatus in the first Example of the second Embodiment.

FIG. 16 is a diagram illustrating the potential of the imaging region ofthe imaging apparatus in the first Example of the second Embodiment.

FIG. 17 is an example cross-sectional diagram corresponding with theparts illustrated in FIG. 16.

FIG. 18 is another example cross-sectional diagram corresponding withthe parts illustrated in FIG. 16.

FIG. 19 is an equivalent circuit diagram illustrating the first pixel ofthe imaging region of the imaging apparatus in a second Example of thesecond Embodiment.

FIG. 20 is a diagram illustrating control pulses corresponding to theimaging region of the imaging apparatus in the second Example of thesecond Embodiment.

FIG. 21A is a diagram illustrating control pulses corresponding to theimaging region of the imaging apparatus in the second Example of thesecond Embodiment.

FIG. 21B is a diagram illustrating control pulses corresponding to theimaging region of the imaging apparatus in the second Example of thesecond Embodiment.

FIG. 22 is a cross-sectional diagram illustrating the first pixel of theimaging region of the imaging apparatus in a third Example of the secondEmbodiment.

FIG. 23A is a cross-sectional diagram illustrating the first pixel inthe imaging region of the imaging apparatus in a fourth Example of thesecond Embodiment, and FIG. 23B is a diagram illustrating the potentialof the parts illustrated in FIG. 23A.

FIG. 24 is a top view of the imaging region of the imaging apparatus ina fifth Example of the second Embodiment.

FIG. 25 is an equivalent circuit diagram illustrating the first pixel ofthe imaging region of the imaging apparatus in the fifth Example of thesecond Embodiment.

FIG. 26 is a diagram illustrating control pulses corresponding to theimaging region of the imaging apparatus in the fifth Example of thesecond Embodiment.

FIG. 27 is a top view of an imaging region of an imaging apparatus in asixth Example of the second Embodiment.

FIG. 28 is an equivalent circuit diagram illustrating the imaging regionof the imaging apparatus in the sixth Example of the second Embodiment.

FIG. 29A is a cross-sectional diagram illustrating the first pixel ofthe imaging apparatus in the sixth Example of the second Embodiment.FIG. 29B is a diagram illustrating the potential of the partsillustrated in FIG. 29A.

FIG. 30A is a diagram illustrating control pulses corresponding to theimaging region of the imaging apparatus in the sixth Example of thesecond Embodiment.

FIG. 30B is a diagram illustrating control pulses corresponding to theimaging region of the imaging apparatus in the sixth Example of thesecond Embodiment.

FIG. 31 is an equivalent circuit diagram illustrating the first pixel ofthe imaging apparatus in a seventh Example of the second Embodiment.

FIG. 32 is a diagram illustrating control pulses corresponding to theimaging region of the imaging apparatus in the seventh Example of thesecond Embodiment.

FIG. 33 is a top view of the imaging region of the imaging apparatus inan eighth Example of the second Embodiment.

FIG. 34 is an equivalent circuit diagram illustrating the first pixel ofthe imaging apparatus in the eighth Example of the second Embodiment.

FIG. 35 is a diagram illustrating control pulses corresponding to theimaging region of the imaging apparatus in the eighth Example of thesecond Embodiment.

FIG. 36 is a diagram illustrating control pulses corresponding to theimaging region of the imaging apparatus in the eighth Example of thesecond Embodiment.

FIG. 37 is an equivalent circuit diagram of the first pixel of theimaging region in a ninth Example of the second Embodiment.

FIG. 38 is a diagram illustrating control pulses corresponding to theimaging region of the imaging apparatus in the ninth Example of thesecond Embodiment.

FIG. 39 is a diagram explaining a focal point detection mechanism.

FIGS. 40A and 40B are diagrams explaining the focal point detectionmechanism.

FIG. 41 is a block diagram of an imaging system using the imagingapparatus.

DESCRIPTION OF THE EMBODIMENTS

The present technology is divided into two embodiments. Each embodimentincludes multiple examples. The first Embodiment is a configuration withdistinctly different pixels for focal point detection and pixels forimaging, in which to perform a phase contrast detection type of focalpoint detection on an imaging face. For example, the aperture of thefocal point detection pixels is narrower than the aperture of theimaging pixels. The focal point detection pixels include alight-shielding member, and are configured such that an orthogonallyprojected image of the light-shielding member as to a photoelectricconversion unit partially overlaps the photoelectric conversion unit.

The second Embodiment is a configuration for performing the phasecontrast detection type of focal point detection on the imaging face, inwhich the configuration includes multiple photoelectric conversion unitsthat correspond to one microlens in one pixel, and so focal pointdetection is performed by using each of the signals from multiplephotoelectric conversion units.

While the present technology will be described here by way of the firstEmbodiment and the second Embodiment, the present technology may beapplicable to portions of other embodiments without departing from thescope of the present technology. For example, the first Embodiment hasdifferent pixel configurations for imaging pixels and for focal pointdetection pixels. The configuration of pixels in the second Embodimentmay be used in an imaging apparatus that includes the focal pointdetection mechanism of the first Embodiment, and so details for thesekinds of configurations will be described for each embodiment.

First Embodiment First Example

FIG. 1 is a top view of a portion of an imaging region of an imagingapparatus in the first Example of the first Embodiment. The imagingregion of the imaging apparatus in the present embodiment has bothimaging pixels and focal point detection pixels, which output signalsfor performing focal point detection, and these pixels are disposed inan array.

Multiples pixels 101, 101 a, 101 b, 101 c, and 101 d are disposed in anarray on an imaging region 100. Circles in FIG. 1 represent microlenses.Squares within the circles represent the aperture of each pixel.

The first pixel 101 is an imaging pixel. Its aperture is wider ascompared to other pixels. The aperture of a second pixel 101 a isnarrower than that of the first pixel 101, and the region of theaperture of the first pixel 101 on the right side of FIG. 1 is shieldedfrom light. The aperture of a third pixel 101 b is narrower than that ofthe first pixel 101, and the region of the aperture of the first pixel101 on the left side of FIG. 1 is shielded from light. The second pixel101 a and the third pixel 101 b enable the phase contrast detection typeof focal point detection to be performed by pupil slicing.

The aperture of a fourth pixel 101 c is narrower than that of the firstpixel 101, and the region of the aperture of the first pixel 101 on thebottom side of FIG. 1 is shielded from light. The aperture of a fifthpixel 101 d is narrower than that of the first pixel 101, and the regionof the aperture of the first pixel 101 on the top side of FIG. 1 isshielded from light. The fourth pixel 101 c and the fifth pixel 101 denable the phase contrast detection type of focal point detection to beperformed by pupil slicing.

FIG. 2 illustrates an expanded top view of the imaging region of theimaging apparatus in the present embodiment. The first pixel 101 and thesecond pixel 101 a are adjacent with each other in the regionillustrated here. FIG. 3 illustrates an example equivalent circuitdiagram of pixels in the present embodiment. The members denoted withthe same reference numerals in FIGS. 2 and 3 have the same functions.Members denoted with the same numerals in FIG. 2 have the same functionsin both the first pixel and the second pixel. Configuration elements ofthe second pixel are denoted with a reference code A to distinguishbetween the first pixel and the second pixel. Only those portions of thesecond pixel that differ from the first pixel will be described.

An electron hole is generated when light illuminates on thephotoelectric conversion unit PD. A first signal holding unit MEM1 isconfigured to hold a charge to be used as a signal charge from theelectron hole. The following describes cases where electrons are used asthe signal charge. A first charge transfer unit TX1 is disposed in theelectrical pathway between the photoelectric conversion unit PD and thefirst signal holding unit MEM1.

The electrons held at the first signal holding unit MEM1 are transferredto a floating diffusion FD via a second charge transfer unit TX2. FD iselectrically connected to an input node of an amplification transistorSF in the pixel. The floating diffusion FD may also be configured withthe input node of the amplification transistor SF. A selectiontransistor SEL is disposed in the electrical pathway between theamplification transistor SF and a vertical signal line VOUT. Pixels readout from each vertical signal line VOUT are selected by the selectiontransistor SEL. A reset transistor RES performs resets by supplying areference voltage to a gate of the amplification transistor SF. Anoverflow drain control unit (hereafter OFD control unit) TX4 drainselectrons generated at the photoelectric conversion unit PD to an OFDregion 210.

A control pulse φTX1 is supplied to the first charge transfer unit TX1.A control pulse φTX2 is supplied to the second charge transfer unit TX2.A control pulse φOFD is supplied to the OFD control unit TX3. A controlpulse φSEL is supplied to the gate of the selection transistor SEL. Acontrol pulse φRES is supplied to the gate of the reset transistor RES.

The first pixel through the fifth pixel may have the same equivalentcircuit. What is different between the first pixel through the fifthpixel is the shape of the light-shielding member disposed on thephotoelectric conversion unit PD. Specifically, the shapes are differentas illustrated in FIG. 1.

FIG. 4A is a cross-sectional diagram illustrating the first pixel of theimaging apparatus in the present embodiment. This illustrates thecross-section of IVA-IVA in FIG. 2. FIG. 4B is a diagram illustratingthe potential of the parts illustrated in FIG. 4A.

The photoelectric conversion unit PD, the first signal holding unitMEM1, an FD region FD, and others are configured by disposing multipleN-type semiconductor regions in a P-type semiconductor region 401. TheP-type semiconductor region 401 may use a P-type semiconductorsubstrate, or may use a P-type semiconductor region formed by ionimplantation in an N-type semiconductor substrate.

The photoelectric conversion unit PD includes a P-type conductor region401, an N-type semiconductor region 402 disposed to configure a PNjunction with the P-type semiconductor region 401, and a P-typesemiconductor region 403 disposed on the N-type semiconductor region402. The photoelectric conversion unit PD is configured as a so-calledembedded photodiode.

The first charge transfer unit TX1 includes a first control electrode404 and a first channel disposed in the lower portion of the firstcontrol electrode 404 via an insulating layer. Here, the first channelis configured from a portion of the P-type semiconductor region 401.Further, the height of the potential barrier of the first channel isadjusted by implanting impurity ions in the P-type semiconductor region401.

The first signal holding unit MEM1 is configured with the inclusion of asecond control electrode 406, and an N-type semiconductor region 405disposed in the lower portion of the second control electrode 406 via aninsulating layer. It is preferable if the voltage of the second controlelectrode 406 is controlled by negative voltage during accumulation inorder to stop the generation of dark current on the face of the N-typesemiconductor region 405. During transfers from the photoelectricconversion unit to the first signal holding unit MEM1, the applicationof a positive voltage, when desired and appropriate, may improvetransfer properties.

The second charge transfer unit TX2 includes a third control electrode407 and a second channel disposed in and the lower portion of the thirdcontrol electrode 407 via an insulating layer. Here, the second channelis configured from a portion of the P-type semiconductor region 401.Further, the height of the potential barrier of the second channel maybe adjusted by implanting impurity ions in the P-type semiconductorregion 401.

The FD region FD includes an N-type semiconductor region 408. The N-typesemiconductor region 408 is electrically connected to the gate of theamplification transistor SF via a plug 409.

The OFD control unit TX4 includes a fourth control electrode 411 and athird channel disposed in the lower portion of the fourth controlelectrode 411 via an insulating layer. Here, the third channel isconfigured as a portion of the P-type semiconductor region 401. Further,the height of the potential barrier of the third channel may be adjustedby implanting impurity ions in the P-type semiconductor region 401.

The OFD region OFD includes an N-type semiconductor region 412. TheN-type semiconductor region 412 is electrically connected to a powersupply line via a plug 413.

A light-shielding member 410 is disposed on the first signal holdingunit MEM1. It is more desirable for the second control electrode 406 tobe included in the orthogonal projection toward the second controlelectrode 406 of the light-shielding member 410. Further, it ispreferable if the light-shielding member 410 is disposed so that itextends onto the first control electrode 404 until the side wall of thephotoelectric conversion unit PD side of the first control electrode404. Further, a light-shielding member 411 may extend to other members,or may extend onto the second charge transfer unit TX2 and the fourthcontrol electrode 411.

FIG. 4B is a diagram illustrating the potential state whennon-electroconducting control pulses are supplied to the first controlelectrode through the fourth control electrode. That is to say, this isthe state when the control pulse with the highest electron potentialfrom among the control pulses supplied to the first control electrodethrough the fourth control electrode is supplied. Such a potential stateis, for example, a period when, after signals from all pixels for thenth frame are transferred to the first signal holding unit MEM1simultaneously, electrons are accumulated in the photoelectricconversion unit PD and the first signal holding unit MEM1 during aperiod until the second charge transfer unit TX2 is scanned per row.

FIG. 5 is a total block diagram illustrating the imaging apparatus inthe present example. The functions that are the same as those in FIG. 1through FIG. 4 are denoted with the same reference numerals, and thustheir descriptions are omitted here. Three rows by three columns ofpixels are illustrated in FIG. 5 for a total of 9 pixels, but many morepixels may be disposed. Also, regarding the arrangement of the firstthrough the fifth pixels, the first pixel 101, the second pixel 101 a,and the third pixel 101 b are disposed in the first row; and the firstpixel 101 a, the fourth pixel 101 c, and the fifth pixel 101 d aredisposed in the second row. Further, the first pixel 101, the secondpixel 101 a, and the third pixel 101 b are disposed in the third row.

The control pulses are supplied from a vertical scanning unit 501 perpixel row, or at intervals of multiple pixel rows. The vertical scanningunit 500 may be configured with a shift register and an address decoder.

A column circuit 502 is configured with multiple circuit blocks thatcorrespond to each of the pixel rows. Each circuit block includes afirst switch 503 controlled by a control pulse φTS, and a second switch504 controlled by a control pulse φTN. Further, an optical signalholding unit 505 is disposed downstream of the first switch 503, and anoise signal holding unit 506 is disposed downstream of the secondswitch 504. Also, the optical signal holding unit 505 is disposeddownstream of a third switch 507, and the noise holding unit 506 isdisposed downstream of a fourth switch 508. The third switch 507 and thefourth switch 508 are controlled by a PHSEL. A horizontal signal lineSENSOR_OUT_S is disposed downstream of the third switch 507, and ahorizontal signal line SENSOR_OUT_N is disposed downstream of the fourthswitch 508.

The signal transfer scenario for such a total block diagram will bedescribed next. Multiple pixels included in a predetermined pixel roware reset, and during a period where noise signals may be output andmultiple pixels in a predetermined pixel row are selectable by thevertical scanning unit 501, noise signals are output to the verticalsignal line VOUT. The noise signals are offset noise from the pixeltransistors or random noise. They may also be noise signals from thecolumn circuit.

The noise signals transferred on the vertical signal line VOUT are heldin the noise holding unit 506 via the second switch 504. Afterwards, thesignals based on the charges generated by the photoelectric conversionunits in the multiple pixels change to a state where they may be output.Also, during the period where the multiple pixels in the predeterminedrow are in a selectable state by the vertical scanning unit 501, anoptical signal with the noise signals superimposed in the verticalsignal line (hereafter, referred to simply as “optical signal”) isoutput.

The noise signals transferred on the vertical signal line VOUT are heldin the noise holding unit 505 via the first switch 503. Afterwards, theoptical signal and noise signal are output in phase to the horizontaloutput line SENSOR_OUT_S and SENSOR_OUT_N, by the third switch and thefourth switch being changed to an electroconductive state by the PHSELper row or for intervals of multiple rows. Noise may be removed whenthese signals are processed by a signal processing circuit notillustrated.

FIG. 6 illustrates more specific control pulses. All control pulses areat a high level and in an electroconductive state.

Until a timing T1, the φRES of all pixels on the imaging face are at ahigh level, and the reference voltage has been supplied to the gate ofthe amplification transistor. Other control pulses illustrated in FIG. 6are at a low level.

At the timing T1, the φTX1, φTX2, φOFD of all pixels on the imaging facechange from a low level to a high level, and at a timing T2, the φTX1,φTX2, φOFD of all pixels on the imaging face change from a high level toa low level. Such an operation enables the electrons in thephotoelectric conversion unit PD and the first signal holding unit MEM1to be drained to the reset transistor RES drain via the OFD region orthe FD region. Also at the timing T2, the imaging exposure period of thenth frame begins. As illustrated in FIG. 6, the exposure period is thesame for the entire imaging face.

At a timing T3, the φTX1 of all pixels on the imaging face changes froma low level to a high level, and at a timing T4, the φTX1 of all pixelson the imaging face changes from a high level to a low level. Such anoperation enables the electrons in the photoelectric conversion unit PDfor all pixels on the imaging face to be transferred simultaneously tothe first signal holding MEM1.

At a timing T5, the φOFD of all pixels on the imaging face change from alow level to a high level, and electrons generated by the illuminationof light on the photoelectric conversion unit PD are drained to the OFDregion.

Next, at a timing T6, a φSEL_1 changes from a low level to a high level.At the same time, a φRES_1 changes from a high level to a low level.Such an operation enables pixel noise signals to be output to thevertical signal line VOUT.

At a timing T7, a PTN changes from a low level to a high level, and at atiming T8, the PTN changes from a high level to a low level. Such anoperation enables the noise signals for the first row of pixels to beheld in the noise signal holding unit 506 in the column circuit.

At a timing T9, a φTX2_1 changes from a low level to a high level. At atiming T10, the φTX2_1 changes from a high level to a low level. Such anoperation enables electrons for the multiple pixels in the first row tobe transferred from the first signal holding MEM1 to the gate of theamplification transistor SF.

At a timing T11, the PTS changes from a low level to a high level, andat a timing T12, the PTS changes from a high level to a low level. Suchan operation enables the optical signal from the pixels in the first rowto be held in the optical signal holding unit 505 in the column circuit.

Next, at timings T13 through T19, PHSEL_1 through PHSEL_3 areconsecutively changed to an electroconductive state, which enablessignals of each pixel row to be consecutively output to the horizontaloutput line. This period is called the horizontal scanning period(horizontally enabled period). The optical signals and the noise signalsare simultaneously output in units of rows.

At a timing T20, a φSEL1 changes from a high level to a low level. Thepixels in the first row change from a selectable state to anon-selectable state. In continuance, at timings T21 through T33, thesignals from the pixels in the second row are read out in the same wayas those in the first row.

Next, at timings from T34, the signals from the pixels in the third roware read out. Regarding the present example, the exposure period of thenext frame begins during the read out period of the pixels in the thirdrow. At a timing T35, the φOFD of all pixels on the imaging face changefrom a high level to a low level. Such an operation enables theelectrons generated from light illuminated on the photoelectricconversion unit PD to be accumulated in the photoelectric conversionunit PD.

Such operations enable the implementation of a global electron shutter,and further, noise signals generated from each pixel may be removed viaa downstream circuit not illustrated. Also, the focal point detectionsignals may be output while the next frame is accumulated.

Second Example

FIG. 7A is a cross-sectional diagram illustrating the first pixel in thesecond Example of the first Embodiment, and FIG. 7B is a diagramillustrating the potential of the parts illustrated in FIG. 7A. The keycharacteristic of the first Example is the height of the potentialbarrier between the photoelectric conversion unit PD and the firstsignal holding unit MEM1. The configuration enables electrons to betransferred from the photoelectric conversion unit to the first signalholding unit MEM1 when the first charge transfer unit TX1, which isdisposed in the electrical pathway between the photoelectric conversionunit PD and the first signal holding unit MEM1, is in anon-electroconductive state. Here, the non-electroconductive state is astate in which the generated potential barrier is supplied with thehighest pulse value from among the pulse values to be supplied to thefirst charge transfer unit TX1. Thus, it does not have to be so-calledcompletely off, and so includes a state in which some sort of potentialbarrier has occurred as compared to a case where it is completely on.

As a specific configuration example, this may be implemented by using aMOS transistor as the first charge transfer unit TX1, where this MOStransistor has an embedded channel. More generally, the configurationhas a portion that is in a region deeper than the surface, and has anelectron potential barrier lower than the surface when the first chargetransfer unit TX1 is in a non-electroconductive state. In this case, thecontrol pulse supplied to the first charge transfer unit TX1 may be afixed value. In other words, instead of a configuration that switchesbetween an electroconductive state and a non-electroconductive state, aconfiguration with a fixed potential barrier may be used. When light isilluminated on the photoelectric conversion unit PD in such aconfiguration, the majority of electrons generated by the photoelectricconversion are transferred to the first signal holding unit MEM1 duringthe exposure period. Thus, the accumulation period for all pixels on theimaging face may be aligned together.

When the first charge transfer unit TX1 is in a non-electroconductivestate, a hole accumulates in a first channel face of the first chargetransfer unit. Next, as electrons to be transferred are in the firstchannel, whose predetermined depth is deeper than that of the surface,the influence of dark current may be reduced as compared to whenelectrons are transferred on an insulating layer interface.

The first charge transfer unit TX1 in FIG. 7A includes a first controlelectrode 702 and an N-type semiconductor region 703. FIG. 7B is adiagram illustrating the potential of the state when thenon-electroconductive control pulse is supplied to each controlelectrode. In other words, this is the state when the control pulse withthe highest potential from among the control pulses to be supplied toeach control electrode is supplied. This potential state is, forexample, the period when, after the signals from the nth frame aretransferred to the first signal holding unit MEM1, electrons areaccumulated at the photoelectric conversion unit PD and the first signalholding unit until the time that the second charge transfer unit TX2scans each row.

Also, compared to the height of the potential barrier generated by theOFD control unit TX4, the height of the potential barrier generated bythe first charge transfer unit TX1 is lower. Such a configurationenables the N-type semiconductor region 703 to be disposed in proximityto the first channel.

FIG. 8 illustrates an example of control pulses for the imaging regionof the imaging apparatus in the present example. The basic operation isthe same as that of FIG. 6. Compared to the operation in FIG. 6 however,the height of the potential barrier of the first charge transfer unitTX1 is lower. Thus, during the period in which electrons are held in thefirst signal holding unit MEM1, the φOFD remains at a high level, whichthen is controlled to drain the electrons generated by the photoelectricconversion unit PD to the OFD region. Specifically, the timing T3, whichstarts the exposure period of the N+1 frame, is set to execute after allpixel rows on the imaging face for the nth frame are read out.

Further, it is preferable if the low level state of the φTX1 is anegative voltage. This decreases dark current by gathering holes on theface of the N-type semiconductor region 405 of the first charge holdingunit MEM1.

Second Embodiment First Example

FIG. 9 is a top view of the imaging region of the imaging apparatus inthe present example. The difference with the first Embodiment is thatwhile different pixels are used to configure the imaging pixels and thefocal point detection pixels for the first Embodiment, in the presentexample, the first pixel is divided with multiple photoelectricconversion units, and focal point detection is performed by usingsignals from these multiple photoelectric conversion units. The pixelshere are imaging pixels of the smallest unit. For example, whenincluding a microlens array that includes multiple microlenses, onemicrolens is the unit of measurement that represents one pixel. That isto say, this configuration includes multiple photoelectric conversionunits to receive light condensed by one microlens, which is then able toextract the signals from each photoelectric conversion unitindependently. Multiple methods to independently extract each signal maybe conceived, and processing is performed at a downstream circuit toenable such a configuration.

In FIG. 9, two photoelectric conversion units are disposed to correspondto a single microlens. This is illustrated as a first photoelectricconversion unit A and a second photoelectric conversion unit B. Allpixels in FIG. 9 include two photoelectric conversion units which arejuxtaposed horizontally therein. However, they may be juxtaposedvertically as well, and pixels with photoelectric conversion unitsjuxtaposed horizontally and pixels with photoelectric conversion unitsjuxtaposed vertically may be mixed together.

FIG. 10 is a top view of the pixels in the present example. Here, threeadjacent pixels are illustrated. Many more pixels may be arranged.

The first photoelectric conversion unit PD_A is adjacent to the secondphotoelectric conversion unit PD_B, on which light condensed by the onemircrolens per unit is illuminated. Electrons generated at eachphotoelectric unit are transferred to and held at first signal holdingunits MEM_A and MEM_B via the first charge transfer unit TX1. Othertransistors and similar that configure pixel circuits are disposed in aregion disposed in the lower section of FIG. 10. Electrons generated atthe photoelectric conversion units PD_A and PD_B may be drained to theOFD region.

FIG. 11 is an equivalent circuit diagram illustrating the first pixel ofthe present example. The functions that are the same as those in FIG. 10are denoted with the same reference numerals, and thus theirdescriptions are omitted here. A circuit is provided for the firstphotoelectric conversion unit PD_A, and another circuit is provided forthe second photoelectric conversion unit PD_B. Also, multiple verticalsignal lines are provided for each pixel row. In the present example,two vertical signal lines are provided for each pixel row. Each of theseoperations is similar, and so only the pixel circuit for the firstphotoelectric conversion unit PD_A will be described.

An electron hole is generated when light illuminates on thephotoelectric conversion unit PD_A. The first charge transfer unit TX1_Ais disposed in an electrical pathway between the first photoelectricconversion unit PD_A and the first signal holding unit MEM_A.

The electrons held at the first signal holding unit MEM_A aretransferred to an input node of an amplification transistor SF_A via asecond charge transfer unit TX2_A. The input node includes an FD. Theselection transistor SEL is disposed in an electrical pathway betweenthe amplification transistor SF_A and a vertical signal line VOUT_A.Pixels read out to the vertical signal line VOUT_A are selected by theselection transistor SEL_A. A reset transistor RES_A performs resets bysupplying a reference voltage to the input node of the amplificationtransistor SF_A. An OFD control unit OFD_A drains electrons generated atthe first photoelectric conversion unit PD_A to the OFD region.Particularly, it is preferable if the OFD control unit OFD_A operateswhen during the period when signal charges for generating the focalpoint detection signals are accumulating at the first signal unit MEM1.

The control pulse φTX1 is supplied to the first charge transfer unitTX1_A. The control pulse φTX2 is supplied to the first charge transferunit TX2. The control pulse φOFD is supplied to the OFD control unitOFD_A. The control pulse φSEL is supplied to the gate of the selectiontransistor SEL_A. The control pulse φRES is supplied to the gate of thereset transistor RES_A.

It should be noted here that the control pulse supplied to each controlelectrode and transistor is shared for the same pixel row. Such aconfiguration enables high speed read out of signals as it is possibleto read out focal point detection signals on multiple vertical signallines in parallel. Also, imaging signals are obtained by first beingread out to vertical signal lines VOUT_A and VOUT_B, and then added oraveraged at a signal processing unit.

FIG. 12A is a cross-sectional diagram illustrating a portion of thepixel configuration corresponding to the first photoelectric conversionunit PD_A in the present example. The cross sections of E through F inFIG. 10 are illustrated. FIG. 12B is a diagram illustrating thepotential of the parts illustrated in FIG. 12A. The pixel configurationfor the second photoelectric conversion unit PD_B is basically the same,and accordingly description will be made only with additional noteswhere desirable.

The photoelectric conversion units PD_A and PD_B, the first signalholding units MEM_A and MEM_B, and the FD region are configured by thedisposing of multiple N-type semiconductor regions in a P-typesemiconductor region 1201. The P-type semiconductor region 1201 may usea P-type semiconductor substrate, or a P-type semiconductor formed byion implantation into an N-type semiconductor substrate.

The photoelectric conversion unit PD_A includes the P-type semiconductorregion 1201, the N-type semiconductor region 402 disposed to configurethe PN junction with the −type semiconductor region 401, and the P-typesemiconductor region 403 disposed on the N-type semiconductor region402. The photoelectric conversion unit PD is configured as a so-calledembedded photodiode.

The first charge transfer unit TX1_A includes a first control electrode1204 and a first channel disposed in the lower portion of the firstcontrol electrode 1204 via an insulating layer. The first channel isconfigured as a portion of the P-type semiconductor region 1201.Further, the height of the potential barrier of the first channel may beadjusted by implanting impurity ions in the P-type semiconductor region1201.

The first signal holding unit MEM_A includes a second control electrode1206 and an N-type semiconductor region 1205 disposed in the lowerportion of the second control electrode 1206 via and an insulatinglayer.

The second charge transfer unit TX2_A includes a third control electrode1207 and a second channel disposed in the lower portion of the thirdcontrol electrode 1207 via an insulating layer. The second channel isconfigured as a portion of the P-type semiconductor region 1201.Further, the height of the potential barrier of the second channel maybe adjusted by implanting impurity ions in the P-type semiconductorregion 1201.

The FD region includes an N-type semiconductor region 408. The N-typesemiconductor region 408 is electrically connected to the gate of theamplification transistor via a plug 1209.

The OFD control unit OFD_A includes a fourth control electrode 1211 anda third channel disposed in the lower portion of the fourth controlelectrode 1211 via an insulating layer. The third channel is configuredas a portion of the P-type semiconductor region 1201. Further, theheight of the potential barrier of the third channel may be adjusted byimplanting impurity ions in the P-type semiconductor region 1201.

The OFD region includes an N-type semiconductor region 1212. The N-typesemiconductor region 1212 is electrically connected to a power supplyline via a plug 1213.

A light-shielding member 1210 is disposed on the first signal holdingunit MEM_A. It is more desirable for the second control electrode 1206to be included in the orthogonal projection toward the second controlelectrode 1206 of the light-shielding member 1210. Further, it ispreferable if the light-shielding member 1210 is disposed so that itextends onto the first control electrode 1204 until the side wall of thephotoelectric conversion unit PD_A side of the first control electrode1204. Further, a light-shielding member 1211 may extend to othermembers, or may extend onto the second charge transfer unit TX2_A andthe fourth control electrode 1211.

FIG. 12B is a diagram illustrating the potential state whennon-electroconducting control pulses are supplied to the first controlelectrode through the fourth control electrode. That is to say, this isthe state when the control pulse with the highest electron potentialfrom among the control pulses supplied to the first control electrodethrough the fourth control electrode is supplied. Such a potential stateis, for example, a period when, after signals from all pixels for thenth frame are transferred to the first signal holding unit MEM_Asimultaneously, electrons are accumulated in the photoelectricconversion unit PD_A and the first signal holding unit MEM_A during aperiod until the second charge transfer unit TX2_A is scanned per row.

As can be seen from FIG. 12B, the height of the potential barriergenerated by the first charge transfer unit TX1 is low. As for relativerelationships, for example, this potential barrier is even lower thanthe potential barrier generated by the OFD control unit.

FIG. 13 is a total block diagram illustrating the imaging apparatus ofthe present example. Three rows by three columns of pixels areillustrated in FIG. 13 for a total of 9 pixels, but many more pixels maybe disposed.

Multiple pixels 1301 are disposed in an imaging region 1300. Controlpulses are supplied from a vertical scanning unit 1302 per pixel row orfor intervals of multiple pixel rows. It is preferable if pulses aresent at the same timing to the circuits corresponding to both the firstphotoelectric conversion unit PD_A and the second photoelectricconversion unit PD_B, both of which are included in the same pixel.

The vertical scanning unit 1302 may be configured with a shift registerand an address decoder.

A column circuit 1303 is configured with multiple circuit blocks thatcorrespond to each of the pixel rows. Each circuit block includes firstswitches 1304_A and 1304_B controlled by a control pulse φTS, and secondswitches 1305_A and 1305_B controlled by a control pulse φTN. Further,optical signal holding units 1306_A and 1306_B are disposed downstreamof the first switches 1304_A and 1304_B. Noise signal holding units1307_A and 1307_B are disposed downstream of the second switches 1305_Aand 1305_B. Also, the optical signal holding units 1306_A and 1306_B aredisposed downstream of third switches 1308_A and 1308_B, and the noiseholding units 1307_A and 1307_B are disposed downstream of fourthswitches 1309_A and 1309_B.

The third switches 1308_A and 1308_B and the fourth switches 1309_A and1309_B are controlled by a PHSEL. Horizontal signal lines SENSOR_OUT_S_Aand SENSOR_OUT_S_B are disposed downstream of the third switches 1308_Aand 1308_B. Horizontal signal lines SENSOR_OUT_N_A and SENSOR_OUT_N_Bare disposed downstream of the fourth switches 1309_A and 1309_B.

The signal transfer scenario for such a total block diagram will bedescribed next. The photoelectric conversion units PD_A and PD_B inmultiple pixels included in a predetermined pixel row are reset toenable a period where noise signals may be output. Next, during a periodwhere multiple pixels in a predetermined pixel row are selectable by thevertical scanning unit 1302, noise signals are output to the verticalsignal lines VOUT_A and VOUT_B. These noise signals are output to thevertical noise signal lines VOUT_A and VOUT_B nearly simultaneously.

The noise signals are offset noise from the pixel transistorscorresponding to each photoelectric conversion unit, or random noise.They may also be noise signals from the column circuit.

The noise signals transferred on the vertical signal lines VOUT_A andVOUT_B are held in the noise holding units 1307_A and 1307_B via thesecond switches 1305_A and 1305_B nearly simultaneously. Afterwards, thesignals based on the charge generated at the photoelectric conversionunits PD_A and PD_B of the multiple pixels included in the predeterminedpixel row change to a state where they may be output. Also, during theperiod where the multiple pixels in the predetermined row are in aselectable state by the vertical scanning unit 1302, an optical signalwith the noise signals superimposed in the vertical signal line(hereafter, referred to simply as “optical signal”) is output to thevertical signal lines VOUT_A and VOUT_B nearly simultaneously.

The optical signals transferred on the vertical signal lines VOUT_A andVOUT_B are held in the optical signal holding units 1306_A and 1306_Bvia the first switches 1304_A and 1304_B nearly simultaneously.Afterwards, the optical signal and noise signal are output in phase tocorresponding horizontal output lines, by the third switch and thefourth switch being changed to an electroconductive state by the PHSELper row or for intervals of multiple rows. Noise may be removed whenthis signal is processed by a signal processing circuit not illustrated.

FIG. 14 illustrates more specific control pulses. All control pulses areat a high level and in an electroconductive state.

Until a timing T1, the φRES of all pixels on the imaging face are at ahigh level, and the reference voltage has been supplied to the gate ofthe amplification transistor. Other control pulses illustrated in FIG.14 are at a low level. Also, a shared control pulse is supplied to eachcircuit element which has the same function as that of the pixelcircuits for the first photoelectric conversion unit PD_A and the pixelcircuits for the second photoelectric conversion unit PD_B for the samepixel row. That is to say, for the same pixel row, the signals from thefirst photoelectric conversion unit PD_A and the second photoelectricconversion unit PD_B are simultaneously output to the vertical signallines VOUT_A and VOUT_B.

At the timing T1, the φTX1, φTX2, φOFD of all pixels on the imaging facechange from a low level to a high level, and at a timing T2, the φTX1,φTX2, φOFD of all pixels on the imaging face change from a high level toa low level. Such an operation enables the electrons in the firstphotoelectric conversion unit PD_A, the second photoelectric conversionunit PD_B, and the first signal holding units MEM_A and MEM_B to bedrained to the reset transistor drain via the OFD region or the FDregion. Also at the timing T2, the imaging exposure period of the nthframe begins. As illustrated in FIG. 14, the exposure period is the samefor the entire imaging face.

At a timing T3, the φTX1 of all pixels on the imaging face changes froma low level to a high level, and at a timing T4, the φTX1 of all pixelson the imaging face changes from a high level to a low level. Such anoperation enables the electrons in the photoelectric conversion unitPD_A to be transferred to the first signal holding unit MEM_A, for allpixels on the imaging face simultaneously. Similarly, the electrons inthe second photoelectric conversion unit PD_B are transferred to thefirst signal holding unit MEM_B, for all pixels on the imaging facesimultaneously.

At a timing T5, the φOFD of all pixels on the imaging face change from alow level to a high level, and electrons generated by the lightilluminated on the photoelectric conversion units PD_A and PD_B aredrained to the OFD region. The OFD operation should be run period whensignal charges for generating focal point detection signals are held inthe first signal holding unit MEM1.

Next, at a timing T6, a φSEL_1 changes from a low level to a high level,and at the same time, a φRES_1 changes from a high level to a low level.Such an operation enables pixel noise signals to be output to thevertical signal lines VOUT_A and VOUT_B.

At a timing T7, a PTN changes from a low level to a high level, and at atiming T8, the PTN changes from a high level to a low level. Such anoperation enables the noise signals for the first row of pixels to beheld in the noise signal holding units in the column circuit.

At a timing T9, a φTX2_1 changes from a low level to a high level, andat a timing T10, the φTX2_1 changes from a high level to a low level.Such an operation enables signal charges from the multiple pixels in thefirst row to be transferred from the first signal holding units MEM_Aand MEM_B to the input node of the amplification transistors SF_A andSF_B.

At a timing T11, the PTS changes from a low level to a high level, andat a timing T12, the PTS changes from a high level to a low level. Suchan operation enables the optical signal for focal point detection fromthe pixels in the first row to be held in the optical signal holdingunits in the column circuit. Noise signals are superimposed in theseoptical signals for focal point detection.

Next, at timings T13 through T19, PHSEL_1 through PHSEL_3 areconsecutively changed to an electroconductive state, which enablessignals of each pixel row to be consecutively output to the horizontaloutput lines. This period is called the horizontal scanning period(horizontally enabled period).

At a timing T20, a φSEL1 changes from a high level to a low level. Thepixels in the first row change from a selectable state to anon-selectable state. In continuance, during the period of timings T21through T33, the signals from the pixels in the second row are read outin the same way as those in the first row.

Next, at timings from T34, the signals from the focal point detectingpixels in the third row are read out. Regarding the present example, theexposure period of the next frame begins during the read out period ofthe signals for focal point detection from the pixels in the third row.At a timing T35, the φOFD of all pixels on the imaging face change froma high level to a low level. Such an operation enables the signalcharges for generating focal point detection signals, which aregenerated from light illuminated on the photoelectric conversion unitsPD_A and PD_B, to be accumulated in the photoelectric conversion unitsPD_A and PD_B.

Such operations enable the implementation of a global electron shutter,and further, noise signals generated from each pixel may be removed viaa downstream circuit not illustrated.

FIG. 15 is a diagram illustrating the potential of G through Hillustrated in FIG. 10. FIG. 15 describes the magnitude relationshipbetween the potentials of the photoelectric conversion units PD_A andPD_B for the 3 adjacent pixels, and of regions between these units. Ascan be seen from FIG. 15, the height of the potentials generated by theregions between the first photoelectric conversion unit PD_A and thesecond photoelectric conversion unit PD_B in the same pixel are lowerthan the height of potentials generated by regions between photoelectricconversion units of different pixels which have multiple photoelectricconversion units that are adjacent to each other.

The suffix numbers denoting the photoelectric conversion units in FIG.15 indicate which pixel each unit is included in, and so photoelectricconversion units with the same suffix number belong to the same pixel.Units with different numbers belong to different pixels.

Three adjacent pixels are illustrated in FIG. 15. Let us say that fromthe left, these are a first pixel, a second pixel, and a third pixelrespectively. Illustrated in FIG. 15 are a second photoelectricconversion unit PD_B_1 of the first pixel, a first photoelectricconversion unit PD_A_2 and a second photoelectric conversion unit PD_B_2of the second pixel, and a first photoelectric conversion unit PD_A_3 ofthe third pixel. The region between the first photoelectric conversionunit PD_A_2 and the second photoelectric conversion unit PD_B_2 includedin the same pixel (the second pixel) is illustrated as ISO1. The regions(second regions) between the photoelectric conversion units (PD_B_1 andPD_A_2) adjacent to the photoelectric conversion units of differentpixels (first pixel and second pixel, for example) are illustrated asISO2. Also, the minimum values for the potentials in the pathway areillustrated. The height of the potential of the first region ISO1 islower than the height of the potential of the second region ISO2. Such arelationship between potentials has the following advantages.

Let us say that, for example, at least the first photoelectricconversion unit PD_A_2 is saturated by the difference in sensitivity andthe difference in luminance between the first photoelectric conversionunit PD_A_2 and the second photoelectric conversion unit PD_B_2, whichare adjacent to each other and included in the same pixel. At such atime, a portion of the charge generated at the first photoelectricconversion unit PD_A_2 crosses the potential barrier generated by thefirst region ISO1, and transfers to the second photoelectric conversionunit PD_B_2. Not only this, the charge generated at the firstphotoelectric conversion unit PD_A_2 will also transfer to thephotoelectric conversion unit PD_B_1. Further, this charge will alsotransfer to a transistor array region disposed adjacent to the firstphotoelectric conversion unit PD_A_2 not illustrated.

When the first photoelectric conversion unit PD_A_2 is saturated, butthe second photoelectric conversion unit PD_B_2 is not saturated,signals that have a linearity in accordance with the incident light areoutput from the second photoelectric conversion unit PD_B_2 alone. Forthis reason, when these signals are combined, the combined output isdetermined by the output of the second photoelectric conversion unitPD_B_2 from the point where the first photoelectric conversion unitPD_A_2 is saturated, and as a result, the combined output ends up havinga knee characteristic from the point that the first photoelectricconversion unit PD_A_2 is saturated. This phenomenon is noticeable whenthe charge generated after the first photoelectric conversion unitPD_A_2 becomes saturated leaks to parts other than the PD_B_2. This typeof phenomenon may cause situations where the desired combined signal isnot obtainable. By implementing a potential state such as thatillustrated in FIG. 15 to counter this type of phenomenon, chargetransfers more readily to the adjacent photoelectric conversion unit ofthe same pixel, and so a desirable combined signal may be obtained.

FIG. 16 is a diagram illustrating the potential of I through Jillustrated in FIG. 10. FIG. 16 describes the magnitude relationshipbetween the potentials of the first signal holding units for the 3adjacent pixels, and of regions between these units. The suffix numberrepresents the same information as that of FIG. 15.

The region (the third region) between the first signal holding unitMEM_A_2 and the first signal holding unit MEM_B_2 included in the samepixel is illustrated as ISO3. The regions between the first signalholding units adjacent to the first signal holding units of differentpixels are illustrated as ISO4. The height of the potential of the thirdregion ISO3 is the same as the height of the potential of the fourthregion ISO4. That is to say, the potential between the first signalholding units of the same pixel and between those that are adjacent butbelonging to different pixels does not change. This is because whetherthe space between the first signal holding units is the space betweenmultiple first signal holding units of the same pixel, or whether it isthe space between the first signal holding units that are adjacent butbelonging to different pixels, it is desirable to maintain independencebetween these signals. Particularly when using a global electron shutteroperation, if the height of the potential barriers between the thirdregion ISO3 and the fourth region ISO4 is changed, one portion in theimaging face will be different when signals are read out, and this willcause the degree of signal mixing to change.

Further, it is preferable if the height of the potential between thethird region ISO3 and the fourth region ISO4 is higher than the heightof the first region. Further, it is preferable if the height of thepotential between the third region ISO3 and the fourth region ISO4 isthe same as the height of the potential of the second region ISO2.

FIG. 17 is a cross-sectional diagram illustrating the potential of Ithrough J illustrated in FIG. 10. The portions that have the samefunctions as those in FIG. 10 are denoted with the same referencenumerals, and thus their descriptions are omitted here.

Each of the multiple first signal holding units include multiple N-typesemiconductor regions disposed in a P-type semiconductor region 1701.The P-type semiconductor region 1701 may use a P-type semiconductorsubstrate, or may use a P-type semiconductor region formed by ionimplantation in an N-type semiconductor substrate.

The first signal holding unit MEM_B_1 includes an N-type semiconductorregion 1702B_1, and the first signal holding unit MEM_A_2 includes anN-type semiconductor region 1702A_2. Further, the first signal holdingunit MEM_B_2 includes an N-type semiconductor region 1702B_2, and thefirst signal holding unit MEM_A_3 includes an N-type semiconductorregion 1702A_3. The N-type semiconductor regions 1702B_1, 1702A_2,1702B_2, and 1702A_3 are configured with a PN junction to the P-typesemiconductor region 1701. Further, a P-type semiconductor region may bedisposed on the face of each N-type semiconductor region.

The third region ISO3 includes a P-type semiconductor region 1703_3disposed next to an isolating region SiO2 via an insulating layer. Thismay use the so-called channel stop region.

The fourth region ISO4 includes a P-type semiconductor region 1703_4disposed next to an isolating region SiO2 via an insulating layer. Thismay use the so-called channel stop region.

The first charge transfer unit TX1_2 includes a control electrode 1705.The control electrode 1705 is disposed continuously on the N-typesemiconductor regions 1702A_1 and 1702A_2 via an insulating layer. Asillustrated in FIG. 17, this may be disposed on the third region ISO3,which is disposed between the N-type semiconductor regions 1702A_1 and1702A_2.

The first charge transfer unit TX1_2 includes a control electrode 1706.The control electrode 1706 may be disposed in the same way as thecontrol electrode 1705, which is continuously on the N-typesemiconductor regions that correspond to each of the multiple firstsignal holding units included in the same pixel.

According to the configuration in FIG. 17, the height of the potentialfor the third region ISO3 and the fourth region ISO4 may readily beraised due to the provision of element isolating regions, which areimplemented via insulating layers.

FIG. 18 illustrates an example of another cross-section of I through Jillustrated in FIG. 10. The portions that have the same functions asthose in FIG. 10 are denoted with the same reference numerals, and thustheir descriptions are omitted here. The biggest difference from theconfiguration in FIG. 17 is the configuration of the third region ISO3and the fourth region ISO4. Specifically, the element isolating regionimplemented via the insulating layers are not provisioned, and so theconfiguration only contains the semiconductor regions.

Each of the multiple first signal holding units includes multiple N-typesemiconductor regions disposed in a P-type semiconductor region 1801.The P-type semiconductor region 1801 may use a P-type semiconductorsubstrate, or may use a P-type semiconductor region formed by ionimplantation in an N-type semiconductor substrate.

The first signal holding unit MEM_B_1 includes an N-type semiconductorregion 1802B_1, and the first signal holding unit MEM_A_2 includes anN-type semiconductor region 1802A_2. The first signal holding unitMEM_B_2 includes an N-type semiconductor region 1802B_2, and the firstsignal holding unit MEM_A_3 includes an N-type semiconductor region1802A_3. The N-type semiconductor regions 1802B_1, 1802A_2, 1802B_2, and1802A_3 are configured with a PN junction to the P-type semiconductorregion 1801. Further, a P-type semiconductor region may be disposed onthe face of each N-type semiconductor region.

The third region ISO3 includes a P-type semiconductor region 1803_3.Here, one of the semiconductor regions may be configured from multipleregions disposed with different depths as illustrated in FIG. 18.

The fourth region ISO4 includes a P-type semiconductor region 1803_4.Similar to the third region ISO3, this may be configured from regionsdisposed with different depths via multiple processes.

The first charge transfer unit TX1_2 includes control electrodes 1805Aand 1805B. The control electrode 1805A is disposed on the N-typesemiconductor region 1802A_2 via an insulating layer. The controlelectrode 1805B is disposed on the N-type semiconductor region 1802B_2via an insulating layer.

The first charge transfer units TX1_1 and TX1_3 each include a controlelectrode 1806. The control electrode 1806 is disposed on an N-typesemiconductor region which configures the corresponding first signalholding unit.

According to the configuration in FIG. 18, there are few depressions onthe surface of the semiconductor substrate, and so it is easy to disposelight-shielding members. Also, illumination of light transmitted throughinsulating layers, which would be disposed between adjacent pixels, maybe prevented even without any coating of a light-shielding layer thusimproving light-shielding properties. Also, the element isolating unitelectrodes are eliminated, which decreases the area of holding unitelectrodes, and this enables relatively high-speed propagation ofdriving pulses.

Second Example

FIG. 19 illustrates an example of an equivalent circuit for a pixel inthe first Example of the second Embodiment. The portions that have thesame functions as those in FIG. 11 are denoted with the same referencenumerals, and thus their descriptions are omitted here. The differencebetween the present example and the example in FIG. 11 is that theamplification transistor SF is shared between the multiple photoelectricconversion units PD_A and PD_B of the same pixel. Thus, it is desirableto have a configuration where the second charge transfer unit TX2_Acorresponding to the first photoelectric conversion unit PD_A and thesecond charge transfer unit TX2_B corresponding to the firstphotoelectric conversion unit PD_B are independently controllable.

FIG. 20 is a diagram illustrating control pulses for the imagingapparatus in the present example. The driving pulses illustrated in FIG.20 for this example are signals from the multiple photoelectricconversion units of the same pixel which are added at the input node ofthe amplification transistor. Further, a pulse PTS is a control pulseused when signals are held in the photoelectric conversion unit disposedin the column circuit. A pulse PTN is a control pulse used when signalsare held in the noise signal holding unit disposed in the columncircuit. A pulse PHSEL is a control pulse output from the horizontalscanning circuit, and is used for the read out of signals from each rowheld in the column circuit to the horizontal signal lines. The drivingpulses in FIG. 20 may be used in a still image mode.

Until a timing T1, the φRES of all pixels on the imaging face are at ahigh level, and the reference voltage has been supplied to the gate ofthe amplification transistor. Other control pulses illustrated in FIG.20 are at a low level.

At the timing T1, the φTX1, φTX2_A, φTX2_B, and φOFD of all pixels onthe imaging face change from a low level to a high level, and at atiming T2, the φTX1, φTX2_A, φTX2_B, and φOFD of all pixels on theimaging face change from a high level to a low level.

Such an operation enables the electrons in the first photoelectricconversion unit PD_A, the second photoelectric conversion unit PD_B, andthe first signal holding units MEM_A and MEM_B to be drained to thereset transistor drain via the OFD region or the FD region. Also at thetiming T2, the imaging exposure period of the nth frame begins. Asillustrated in FIG. 20, the exposure period is the same for the entireimaging face.

At a timing T3, the φTX1 of all pixels on the imaging face changes froma low level to a high level, and at a timing T4, the φTX1 of all pixelson the imaging face changes from a high level to a low level. Such anoperation enables the signal charges for imaging in the firstphotoelectric conversion unit PD_A to be transferred to the first signalholding MEM_A, for all pixels on the imaging face simultaneously.Similarly, the signal charges for imaging in the second photoelectricconversion unit PD_B are transferred to the first signal holding unitMEM_B, for all pixels on the imaging face simultaneously.

At a timing T5, the φOFD of all pixels on the imaging face change from alow level to a high level, and signal charges generated by lightilluminated on the photoelectric conversion units PD_A and PD_B aredrained to the OFD region.

Next, at a timing T6, a φSEL_1 changes from a low level to a high level,and at the same time, a φRES_1 changes from a high level to a low level.Such an operation enables a state where noise signals may be output tothe vertical signal line VOUT.

At a timing T7, a PTN changes from a low level to a high level, and at atiming T8, the PTN changes from a high level to a low level. Such anoperation enables the noise signals for the first row of pixels to beheld in the noise signal holding units in the column circuit.

At a timing T9, a φTX2_A_1 and a φTX2_B_1 change from a low level to ahigh level, and at a timing T10, the φTX2_A_1 and the φTX2_B_1 changefrom a high level to a low level. Such an operation enables electronsfrom the multiple pixels in the first row to be transferred from thefirst signal holding units MEM_A and MEM_B to the input node of theamplification transistors SF, and then added.

At a timing T11, the PTS changes from a low level to a high level, andat a timing T12, the PTS changes from a high level to a low level. Suchan operation enables the optical signal for imaging from the pixels inthe first row to be held in the optical signal holding units in thecolumn circuit.

Next, at timings T13 through T18, PHSEL_1 through PHSEL_3 areconsecutively changed to an electroconductive state, which enablessignals of each pixel row to be consecutively output to the horizontaloutput lines. This period is called the horizontal scanning period(horizontally enabled period).

At a timing T19, a φSEL1 changes from a high level to a low level, andthe pixels in the first row change from a selectable state to anon-selectable state. In continuance, at timings T20 through T34, thesignals from the pixels in the second row are read out in the same wayas those in the first row.

Next, at timings from T34, the signals from the pixels in the third roware read out. Regarding the present example, the exposure period of thenext frame begins during the read out period of the imaging signals inthe third row. At a timing T35, the φOFD of all pixels on the imagingface change from a high level to a low level. Such an operation enablesthe signal charges generated from light illuminated on the photoelectricconversion units PD_A and PD_B to be accumulated in the photoelectricconversion units PD_A and PD_B. Such operations enable theimplementation of a global electron shutter, and further, noise signalsmay be removed via a downstream circuit not illustrated.

Next, FIGS. 21A and 21B are diagrams illustrating the driving pulsesthat are used for the output of focal point detection signals. Thebiggest difference as compared to the driving pulses in FIG. 20 is thatsignals from the first photoelectric conversion unit PD_A and the secondphotoelectric conversion unit PD_B of the same pixel are independentlyread out to the vertical signal lines. The following describes thedriving pulses focusing on this point in detail.

The period of timings T1 through T8 is the same as that of FIG. 20, andso description thereof is omitted here. FIGS. 21A and 21B combine toform one diagram of the driving pulses where timings T1 through T34 areillustrated in FIG. 21A and timings from T35 are illustrated in FIG.21B.

At a timing T9, a φTX2_A_1 changes from a low level to a high level, andat a timing T10, the φTX2_A_1 changes from a high level to a low level.Such an operation enables signal charges for generating focal pointdetection signals from the multiple pixels in the first row to betransferred from the first signal holding unit MEM_A to the input nodeof the amplification transistor SF.

At a timing T11, the PTS changes from a low level to a high level, andat a timing T12, the PTS changes from a high level to a low level. Suchan operation enables the optical signals for generating focal pointdetection signals from the first photoelectric conversion unit PD_A inthe pixels in the first row to be held in the optical signal holdingunits in the column circuit.

Next, at timings T13 through T18, PHSEL_1 through PHSEL_3 areconsecutively changed to an electroconductive state, which enablessignals of each pixel row to be consecutively output to the horizontaloutput lines. This period is called the horizontal scanning period(horizontally enabled period).

At a timing T19, a φSEL1 changes from a high level to a low level, and aφRES1 changes from a low level to a high level, and at a timing T20, theφSEL1 changes from a low level to a high level, and the φRES1 changesfrom a high level to a low level. Such an operation enables the pixelsin the first row to be temporarily changed to a non-selectable state.Also, a floating state results after the voltage of the input node inthe amplification transistor is reset to the reference voltage. Such anoperation enables the signals of the pixels in the first row to beoutput again to the vertical signal lines.

At a timing T21, the PTN changes from a low level to a high level, andat a timing T22, the PTN changes from a high level to a low level. Suchan operation enables the noise signals from the first row to be held inthe noise signal holding units in the column circuit.

At a timing T23, a φTX2_B_1 changes from a low level to a high level,and at a timing T24, the φTX2_B_1 changes from a high level to a lowlevel. Such an operation enables signal charges for focal pointdetection from the multiple pixels in the first row to be transferredfrom the first signal holding unit MEM_B to the input node of theamplification transistor SF.

At a timing T25, the PTS changes from a low level to a high level, andat a timing T26, the PTS changes from a high level to a low level. Suchan operation enables the optical signals for generating focal pointdetection signals from the second photoelectric conversion unit PD_B inthe pixels in the first row to be held in the optical signal holdingunits in the column circuit.

Next, at timings T27 through T32, PHSEL_1 through PHSEL_3 areconsecutively changed to an electroconductive state, which enablessignals of each pixel row to be consecutively output to the horizontaloutput lines.

At a timing T33, the φSEL1 changes from a high level to a low level. Thepixels in the first row change from a selectable state to anon-selectable state. Such an operation enables the completion of theread out of focal point detection signals of the pixels in the firstrow.

Next, at timings T34 through T62, the focal point detection signals fromthe pixels in the second row are read out in the same way as with thefirst row.

Regarding the present example, the exposure period of the next framebegins during the read out period of the signals for focal pointdetection from the pixels in the third row. At a timing T63, the φOFD ofall pixels on the imaging face change from a high level to a low level.Such an operation enables the signal charges for generating focal pointdetection signals generated from light illuminated on the photoelectricconversion units PD_A and PD_B to be accumulated in the photoelectricconversion units PD_A and PD_B.

Third Example

FIG. 22 is a cross-sectional diagram illustrating the imaging apparatusin the present example. Regarding the cross sections that have beendescribed until this point, the OFD regions have been disposed in thephotoelectric conversion units laterally, i.e., a lateral overflow drain(LOFD) structure. The present example uses a different configurationwhich employs a vertical overflow drain (VOFD).

Power supply voltage is supplied to an N-type semiconductor region 2201,which functions as the VOFD region. A P-type semiconductor region 2202is disposed on the N-type semiconductor region 2201. A P-typesemiconductor region 2203 is disposed on the P-type semiconductor region2202. An N-type semiconductor region 2204 is disposed here to configurea PN junction with the P-type semiconductor region 2203, and a P-typesemiconductor region 2205 is also disposed on the N-type semiconductorregion 2204. The photoelectric conversion unit PD is configured from theP-type semiconductor region 2203, the N-type semiconductor region 2204,and the P-type semiconductor region 2205. This is a so-called embeddedtype of photodiode.

The first charge transfer unit TX1 is configured with a controlelectrode 2211 and a first channel 2206 disposed in the lower portion ofthe control electrode via an insulating layer. The first channel 2206 isconfigured from a portion of the P-type semiconductor region 2203.Further, the height of the potential barrier may be adjusted by theimplantation of impurity ions.

The first signal holding unit MEM1 is configured with the controlelectrode 2211 and an N-type semiconductor region 2207 disposed in thelower portion of the control electrode 2211 via an insulating layer.Negative voltage is supplied to the control electrode to gather holes onthe face of the N-type semiconductor region 2207, which enables thereduction of dark current during the signal holding period at the firstsignal holding unit MEM1.

The second charge transfer unit TX2 is configured with a controlelectrode 2212 and a second channel 2208 disposed in the lower portionof the control electrode 2212 via an insulating layer. The secondchannel 2208 is configured from a portion of the P-type semiconductorregion 2203. Further, the height of the potential barrier may beadjusted by the implantation of impurity ions.

The FD is configured from an N-type semiconductor region 2209. TheN-type semiconductor region 2209 is electrically connected to the gateof the amplification transistor via a plug 2210.

A light-shielding member 2213 is disposed on the first signal holdingunit MEM1. It is more preferable if this extends to the photoelectricconversion unit side of the control electrode 2211.

The operation of the VOFD is performed by the changing of therelationship of the potential of the N-type semiconductor region 2201and P-type semiconductor region 2202 by bias applied externally.Electrons in the N-type semiconductor region 2204 are drained to theN-type semiconductor region 2201. At this time, it is preferable thatelectrons held at the first signal holding unit MEM1 are not drained.That is to say, it is preferable for the transfer of electrons betweenthe N-type semiconductor region 2201 and the N-type semiconductor region2204 to be performed less readily than the transfer of electrons betweenthe N-type semiconductor region 2201 and the N-type semiconductor region2207. As a specific implementation method, a potential barrier may beprovisioned between the N-type semiconductor region 2201 and the N-typesemiconductor region 2207. Further, the distance between the N-typesemiconductor region 2201 and the N-type semiconductor region 2207 maybe longer than the distance between the N-type semiconductor region 2201and the N-type semiconductor region 2204.

Fourth Example

FIG. 23 is a cross-sectional diagram illustrating the imaging apparatusof the present example. The difference between the present example andthe configurations explained until this point is the height of thepotential barrier between the photoelectric conversion unit PD and thefirst signal holding unit MEM1. In other words, the configuration of thefirst charge transfer unit TX1 is different.

The configuration enables electrons to be transferred from thephotoelectric conversion unit PD to the first signal holding unit MEM1when the first charge transfer unit TX1, which is disposed in theelectrical pathway between the photoelectric conversion unit PD and thefirst signal holding unit MEM1, is in a non-electroconductive state.Here, the non-electroconductive state is a state in which the generatedpotential barrier is supplied with the highest pulse value from amongthe pulse values to be supplied to the first charge transfer unit TX1.Thus, it does not have to be so-called completely off, and so includes astate in which some sort of potential barrier has occurred as comparedto a case where it is completely on.

As a specific configuration example, this may be implemented if a MOStransistor is used as the first charge transfer unit TX1, and this MOStransistor has an embedded channel. More generally, the configurationhas a portion that is in a region deeper than the surface, and has anelectron potential barrier lower than the surface when the first chargetransfer unit TX1 is in a non-electroconductive state. In this case, thecontrol pulse supplied to the first charge transfer unit TX1 may be afixed value. In other words, instead of a configuration that switchesbetween an electroconductive state and a non-electroconductive state, aconfiguration with a fixed potential barrier may be used. When light isilluminated on the photoelectric conversion unit PD in such aconfiguration, the greater part of the charge for generating signals forfocal point detection, generated by the photoelectric conversion, istransferred to the first signal holding unit MEM1 during the exposureperiod. Thus, the accumulation period for all pixels on the imaging facemay be aligned together.

Further, when the first charge transfer unit TX1 is in anon-electroconductive state, a hole accumulates on the face. Next, aselectrons to be transferred are in the channel, whose predetermineddepth is deeper than that of the surface, the influence of dark currentmay be reduced as compared to when electrons are transferred on aninsulating layer interface.

Regarding FIG. 23A, photoelectric conversion units PD_A and PD_B, thefirst signal holding units MEM_A and MEM_B, and the FD region areconfigured by the disposing of multiple N-type semiconductor regions onthe P-type semiconductor region 2301. A P-type semiconductor region 2301may use a P-type semiconductor substrate, or may use a P-typesemiconductor region formed by ion implantation in an N-typesemiconductor substrate. Only the first photoelectric conversion unitPD_A and related circuit parts are illustrated in FIG. 23A.

The photoelectric conversion unit PD includes the P-type semiconductorregion 2301, an N-type semiconductor region 2302 disposed to configure aPN junction with the P-type semiconductor region 2301, and a P-typesemiconductor region 2303 that is disposed on the N-type semiconductorregion 2302. This is a so-called embedded type of photodiode.

The first charge transfer unit TX1 includes a first control electrode2312 and a first channel disposed in the lower portion of the firstcontrol electrode 2312 via an insulating layer. Here, the first channelis configured from an N-type semiconductor region 2304.

The first signal holding unit MEM includes the first control electrode2312, and an N-type semiconductor region 2305 disposed in the lowerportion of the first control electrode 2312 via an insulating layer.

The second charge transfer unit TX2 includes a control electrode 2313and a second channel 2306 disposed in the lower portion of the secondelectrode 2313 via an insulating layer. Here, the second channel 2306 isconfigured as a portion of the P-type semiconductor region 2301.Further, the height of the electron potential barrier of the secondchannel 2306 is adjusted by implanting impurity ions in the P-typesemiconductor region 2301.

The FD region includes an N-type semiconductor region 2307. The N-typesemiconductor region 2307 is electrically connected to the gate of theamplification transistor via a plug 2308.

The OFD control unit TX3 includes a third control electrode 2314 and athird channel 2309 disposed in the lower portion of the third controlelectrode 2314 via an insulating layer. Here, the third channel 2309 isconfigured as a portion of the P-type semiconductor region 2301.Further, the height of the electron potential barrier of the thirdchannel 2309 is adjusted by implanting impurity ions in the P-typesemiconductor region 2301.

The OFD region includes an N-type semiconductor region 2310. The N-typesemiconductor region 2310 is electrically connected to a power supplyline via a plug 2311.

A light-shielding member 2315 is disposed on the first signal holdingunit MEM. It is more desirable for the first control electrode 2312 tobe included in the orthogonal projection toward the first controlelectrode 2312 of the light-shielding member 2315. Further, it ispreferable if the light-shielding member 2315 is disposed so that itextends onto the first control electrode 2312 until the side wall of thephotoelectric conversion unit MEM side of the first control electrode2312. Further, the light-shielding member 2315 may extend to othermembers, or may extend onto the second charge transfer unit TX2 and thethird control electrode 2314.

FIG. 23B is a diagram illustrating the potential state whennon-electroconducting control pulses are supplied to the first controlelectrode through the third control electrode. That is to say, this isthe state when the control pulse with the highest electron potentialfrom among the control pulses supplied to the first control electrodethrough the third control electrode is supplied. Such a potential stateis, for example, a period when, after signals from all pixels for thenth frame are transferred to the first signal holding unit MEMsimultaneously, electrons from the nth+1 frame are accumulated in thephotoelectric conversion unit PD during a period until the second chargetransfer unit TX2 is scanned per row.

As can be seen from FIG. 23B, the height of the potential barriergenerated by the first charge transfer unit TX1 is low. As for relativerelationships, for example, this potential barrier is even lower thanthe potential barrier generated by the OFD control unit TX3.

The driving pulses mainly illustrated in FIGS. 14, 20, 21A, and 21B maybe used for this kind of pixel driving, depending on the pixel circuit.However, the difference between these driving pulses is that the OFDcontrol unit TX3 for all pixels on the imaging face has to be in anelectroconductive state during the period when signals are held at thefirst signal holding unit MEM1. This is preferable as such an operationenables the suppression of electrons in the first signal holding unitMEM1 from becoming contaminated.

Fifth Example

FIG. 24 is a top view of the first pixel of the imaging apparatus in thepresent example, and FIG. 25 is an equivalent circuit diagramillustrating the first pixel of the imaging apparatus in the presentexample. The difference between the present example and the examplesdescribed unit above is that the first signal holding unit MEM1 isshared between the first photoelectric conversion unit PD_A and thesecond photoelectric conversion unit PD_B of the same pixel. Theportions that have the same functions as those in the previouslydescribed examples are denoted with the same reference numerals, andthus their descriptions are omitted here.

The basic operation will be described here. First, the equivalentcircuit diagram includes a first charge transfer unit TX1_A to transfersignal charges for generating focal point detection signals at the firstphotoelectric conversion unit PD_A. Further, a first charge transferunit TX1_B is included to transfer signal charges for generating focalpoint detection signals at the second photoelectric conversion unitPD_B. Also, the first charge transfer unit TX1_A and the first chargetransfer unit TX1_B both receive an independent control pulse, and sothis enables a configuration that may operate independently. Incontrast, the OFD control unit OFD_A that drains electrons from thefirst photoelectric conversion unit PD_A and the OFD control unit OFD_Bthat drains electrons from the second photoelectric conversion unit PD_Bmay operate by a shared control pulse.

Such a configuration enables signals based on the signal charges forfocal point detection generated at the first photoelectric conversionunit PD_A and the signals based on the signal charges for focal pointdetection generated at the second photoelectric conversion unit PD_B tobe read out independently on the vertical signal lines.

FIG. 26 is a diagram illustrating an example of driving pulses for theimaging apparatus in the present example. All driving pulses are at ahigh level and in an electroconductive state.

Until a timing T1, the φRES of all pixels on the imaging face are at ahigh level, and the reference voltage has been supplied to the gate ofthe amplification transistor. Other control pulses illustrated in FIG.26 are at a low level.

At the timing T1, the φTX1_A, φTX1_B, φTX2, and φOFD of all pixels onthe imaging face change from a low level to a high level. Next, at atiming T2, the φTX1_A, φTX1_B, φTX2, and φOFD of all pixels on theimaging face change from a high level to a low level. Such an operationenables the charges in the first photoelectric conversion unit PD_A, thesecond photoelectric conversion unit PD_B, and the first signal holdingunit MEM to be drained to the reset transistor drain via the OFD regionor the FD region. Also at the timing T2, the imaging exposure period ofthe nth frame begins. As illustrated in FIG. 26, the exposure period isthe same for the entire imaging face.

At a timing T3, the φTX1_A of all pixels in the first row, the φTX1_B ofall pixels in the second row, and the φTX1_A of all pixels in the thirdrow change from a low level to a high level, and at a timing T4, thesepulses change from a high level to a low level. Such an operationenables the signal charges for generating focal point detection signalsin the first photoelectric conversion unit PD_A for the pixels in thefirst and third row to be transferred to the first signal holding unitMEM. Similarly, the signal charges for generating focal point detectionsignals in the second photoelectric conversion unit PD_B for the pixelsin the second row are transferred to the first signal holding unit MEM.

At a timing T5, the φOFD of all pixels on the imaging face change from alow level to a high level, and electrons generated by light illuminatedon the photoelectric conversion units PD_A and PD_B are drained to theOFD region.

Next, at a timing T6, a φSEL_1 changes from a low level to a high level,and at the same time, a φRES_1 changes from a high level to a low level.Such an operation enables pixel noise signals from the pixels in thefirst row to be output to the vertical signal line VOUT.

At a timing T7, a PTN changes from a low level to a high level, and at atiming T8, the PTN changes from a high level to a low level. Such anoperation enables the noise signals from the first row of pixels to beheld in the noise signal holding units in the column circuit.

At a timing T9, a φTX2_1 changes from a low level to a high level, andat a timing T10, the φTX2_1 change from a high level to a low level.Such an operation enables electrons from the multiple pixels in thefirst row to be transferred from the first signal holding unit MEM tothe input node of the amplification transistor SF.

At a timing T11, the PTS changes from a low level to a high level, andat a timing T12, the PTS changes from a high level to a low level. Suchan operation enables the optical signals for generating focal pointdetection signals generated at the first photoelectric conversion unitPD_A from the pixels in the first row to be held in the optical signalholding units in the column circuit.

Next, at timings T13 through T18, PHSEL_1 through PHSEL_3 areconsecutively changed to an electroconductive state, which enablessignals of each pixel row to be consecutively output to the horizontaloutput lines. This period is called the horizontal scanning period(horizontally enabled period).

At a timing T19, a φSEL1 of the pixels of the first row changes from ahigh level to a low level, and a φRES1 changes from a low level to ahigh level. Such an operation enables the pixels in the first row tochange to a non-selectable state, and the FD and the gate potential ofthe amplification transistor SF are reset by the reset transistor.

At a timing T20, a φSEL1 changes from a high level to a low level, andthe pixels in the first row change from a selectable state to anon-selectable state. In continuance, at timings T21 through T33, thesignals from the pixels in the second row are read out. There is adifference here from the first row. Signals from the pixels based on thesignal charges for generating focal point detection signals generated atthe first photoelectric conversion unit PD_A in the first row are outputto the vertical signal lines. In contrast, signals based on the signalcharges for generating focal point detection signals generated at thesecond photoelectric conversion unit PD_B from the pixels in the secondrow are output.

Next, at timings from T34, the signals from the pixels in the third roware read out. Similarly to those of the first row, the signals based onthe signal charges for generating focal point detection signalsgenerated at the first photoelectric conversion unit PD_A from thepixels in the third row are output.

In other words, signals based on the signal charges for generating focalpoint detection signals generated at the first photoelectric conversionunit PD_A from odd-numbered rows are output. Signals based on the signalcharges for generating focal point detection signals generated at thesecond photoelectric conversion unit PD_B from even-numbered rows arethen output. Of course this may be changed to even-odd rows, or may bechanged randomly per pixel row.

Such an operation enables signals based on the signal charges forgenerating focal point detection signals from the first photoelectricconversion unit PD_A and the second photoelectric conversion unit PD_Bin the same exposure period to be obtained independently from adjacentpixels.

Regarding the present example, the exposure period of the next framebegins during the read out period of the pixels in the third row. At atiming T35, the φOFD of all pixels on the imaging face change from ahigh level to a low level. Such an operation enables the signal chargesfor generating focal point detection signals generated from lightilluminated on the photoelectric conversion units PD_A and PD_B to beaccumulated in the photoelectric conversion units PD_A and PD_B.

Also, if signals from the first photoelectric conversion unit PD_A andthe second photoelectric conversion unit PD_B of the same pixel areadded, during the period for timings T3 through T4, the φTX1_A andφTX2_B of all pixels on the imaging face may be changed to a high levelsimultaneously. Operation may be enabled with the imaging apparatus toswitch between a mode that performs addition of the signals from themultiple photoelectric conversion units of the same pixel, and thedriving pattern illustrated in FIG. 26.

Sixth Example

FIG. 27 is a top view of the imaging apparatus in the present example,and FIG. 28 is an equivalent circuit diagram illustrating the firstpixel of the imaging apparatus in the present example. The portions thathave the same functions as those in the previously described examplesare denoted with the same reference numerals, and thus theirdescriptions are omitted here.

The difference between the present example and the examples described upto this point is that each pixel includes multiple signal holding units,and the signals generated at each photoelectric conversion unit aretransferred consecutively from the multiple signal holding units to theinput node of the amplification transistor. This is specificallydescribed in the circuit diagram in FIG. 28.

Each pixel includes a first charge transfer unit TX1_A to transferelectrons from the first photoelectric conversion unit PD_A and a firstcharge transfer unit TX1_B to transfer electrons from the secondphotoelectric conversion unit PD_B. Also, an output node_1 of both thefirst charge transfer unit TX1_A and TX1_B is electrically connected toan input node_2 of the first signal holding unit MEM1. The first signalholding unit MEM1 includes a node which also has a predetermined voltageapplied. The predetermined voltage may be the ground voltage, forexample.

The second charge transfer unit TX2 transfers signal charges forgenerating focal point detection signals held at the first signalholding unit MEM1 to a second signal holding unit MEM2. Here the outputnode of the second charge transfer unit TX2 is electrically connected toan input node_3 of the second signal holding unit MEM2.

A third charge transfer unit TX3 transfers signal charges for generatingfocal point detection signals held at the second signal holding unitMEM2 to the FD. Also, the FD is electrically connected to the gate ofthe amplification transistor SF. The selection transistor SEL isdisposed electrically between the output node of the amplificationtransistor SF and the vertical signal line VOUT. Further, apredetermined voltage is supplied to the input node of the amplificationtransistor, and the reset transistor RES is disposed to performs resets.

FIG. 29A is a cross-sectional diagram illustrating the first pixel inthe present example. The cross section from the first photoelectricconversion unit PD_A and the cross section from the second photoelectricconversion unit PD_B is the same, and so the following description usesthe first photoelectric conversion unit PD_A as the example. FIG. 27 isa cross-sectional diagram illustrating the portions corresponding to thedotted line.

A P-type semiconductor region 2901 is disposed in an N-typesemiconductor region 2900. An N-type semiconductor region 2902 isdisposed to configure a PN junction with the P-type semiconductor region2901. A P-type semiconductor region 2903 is disposed on the surface sideof the N-type semiconductor region 2902. A so-called embedded type ofphotodiode is configured by the P-type semiconductor region 2901, theN-type semiconductor region 2902, and the P-type semiconductor region2903.

The signal charges for generating focal point detection signalsgenerated at the photoelectric conversion unit PD_A are transferred to afirst channel 2904, and reach an N-type semiconductor region 2905 whichconfigures the first signal holding unit MEM1. The signal charges forgenerating focal point detection signals held at the N-typesemiconductor region 2905 are transferred to a second channel 2906, andreach an N-type semiconductor region 2907 which configures the secondsignal holding unit MEM2. The signal charges for generating focal pointdetection signals held at the N-type semiconductor region 2907 aretransferred to a third channel 2908, and reach an N-type semiconductorregion 2909 which configures the FD region. Also, the signal charges forgenerating focal point detection signals generated at the photoelectricconversion unit PD_A may be drained an N-type semiconductor region 2910which configures the OFD region via a fourth transfer gate 2914.

A first control electrode 2911 is disposed with the first channel 2904and in the upper portion of the N-type semiconductor region 2905 via aninsulating layer. The first control electrode 2911 has dual functions asthe first charge transfer unit TX1 and the first signal holding unitMEM1.

The first charge transfer unit TX1 is configured with the inclusion of aportion of a first control electrode 2911, which is disposed with afirst channel 2904 and via an insulating layer on the first channel2904.

The first signal holding unit MEM1 includes the N-type semiconductorregion (the first semiconductor region) 2905, and the P-typesemiconductor region (the second semiconductor region) 2901 whichconfigures the PN junction with the N-type semiconductor region 2905.Further, the first signal holding unit MEM1 is configured with theinclusion of a portion of the first control electrode 2911 which isdisposed on the N-type semiconductor region 2905 via an insulatinglayer.

A second control electrode 2912 is disposed above the second channel2906 and the N-type semiconductor region 2907 via an insulating layer.The second control electrode 2912 has dual functions as the secondcharge transfer unit TX2 and the second signal holding unit MEM2.

The second charge transfer unit TX2 is configured with the inclusion ofa portion of the second control electrode 2912 which is disposed withthe second channel 2906 and on the second channel 2906 via an insulatinglayer.

The second signal holding unit MEM2 includes the N-type semiconductorregion 2907, and the P-type semiconductor region 2901 which configuresthe PN junction with the N-type semiconductor region 2907. Further, thesecond signal holding unit MEM2 is configured with the inclusion of aportion of the second control electrode 2912 which is disposed on theN-type semiconductor region 2907 via an insulating layer.

A third control electrode 2913 is disposed on the third channel 2908 viaan insulating layer. This is configured with the inclusion of the thirdcharge transfer unit TX3, the third channel 2908, and the third controlelectrode 2913.

FIG. 29B is a diagram illustrating the potential of the cross sectioncorresponding to FIG. 29A. Each control electrode is in anon-electroconductive state, a pulse is supplied. That is to say, theelectron potential barrier is in a high state.

Such a potential state exists during the period when signals are held inthe photoelectric conversion unit PD, the first signal holding unitMEM1, and the second signal holding unit MEM2. The amount of signalcharges that may be held in the first signal holding unit MEM1 isdetermined by the height of the potential generated by the first chargetransfer unit TX1 and the height of the potential generated by thesecond charge transfer unit TX2. Here, the height of the potentialgenerated by the first charge transfer unit TX1 and the height of thepotential generated by the second charge transfer unit TX2 is nearly thesame. Such a state may be implemented by equalizing the concentration ofimpurities in the first channel 2904 and the concentration of impuritiesin the second channel 2906, and by equalizing the amplitude of controlpulses supplied to the first control electrode 2911 and the secondcontrol electrode 2912.

FIGS. 30A and 30B are diagrams illustrating an example of the controlpulses for the imaging region of the imaging apparatus in the presentexample. All control pulses are at a high level and in anelectroconductive state. FIGS. 30A and 30B combine to form one diagramof the driving pulses where timings T1 through T38 are illustrated inFIG. 30A and timings from T39 are illustrated in FIG. 30B. Further, thepulse PTS is a control pulse used to hold signals in the photoelectricconversion unit disposed in the column circuit. The pulse PTN is acontrol pulse used to hold signals in the noise signal holding unitdisposed in the column circuit. The pulse PHSEL is a control pulseoutput from the horizontal scanning circuit, and controls the read outof each row of signals held in the column circuit to the horizontalsignal lines. The driving pulses in FIGS. 30A and 30B may be used in astill image mode.

Until a timing T1, the φRES of all pixels on the imaging face are at ahigh level, and the reference voltage has been supplied to the gate ofthe amplification transistor. Other control pulses illustrated in FIG.30A are at a low level.

At the timing T1, the φTX1_A, φTX1_B, φTX2, φTX3, and φOFD of all pixelson the imaging face change from a low level to a high level. Next, at atiming T2, the φTX1_A, φTX1_B, φTX2, φTX3, and φOFD of all pixels on theimaging face change from a high level to a low level. Such an operationenables the charges in the first photoelectric conversion unit PD_A, thesecond photoelectric conversion unit PD_B, and the first signal holdingunit MEM1 to be drained to the reset transistor drain via the OFD regionor the FD region. Also at the timing T2, the imaging exposure period ofthe nth frame begins. As illustrated in FIG. 30A, the exposure period isthe same for the entire imaging face.

At a timing T3, the φTX1_A of all pixels in the first row on the imagingface change from a low level to a high level, and at a timing T4, theφTX1_A of all pixels in the first row on the imaging face change from ahigh level to a low level. Such an operation enables the signal chargesfor generating focal point detection signals in the first photoelectricconversion unit PD_A for all pixels on the imaging face to betransferred to the first signal holding unit MEM1.

At a timing T5, the φTX2 of all pixels on the imaging face change from alow level to a high level, and at a timing T6, the φTX2 of all pixels onthe imaging face change from a high level to a low level. Such anoperation enables the signal charges for generating focal pointdetection signals held in the first signal holding unit MEM1 to betransferred to the second signal holding unit MEM2 via the second chargetransfer unit TX2.

At a timing T7, the φTX1_B for all pixels on the imaging face changesfrom a low level to a high level, and at a timing T8, the φTX1_B for allpixels on the imaging face changes from a high level to a low level.Such an operation enables the signal charges for generating focal pointdetection signals in the second photoelectric conversion unit PD_B forall pixels on the imaging face to be transferred to the first signalholding unit MEM1.

At a timing T9, the φOFD of all pixels on the imaging face change from alow level to a high level, and the electrons generated from lightilluminated on the photoelectric conversion units PD_A and PD_B aredrained to the OFD region.

At a timing T10, a φSEL_1 changes from a low level to a high level, andat the same time, a φRES_1 changes from a high level to a low level.Such an operation enables the noise signals of pixels in the first rowto be output to the vertical signal line VOUT.

At a timing T11, the PTN changes from a low level to a high level, andat a timing T12, the PTN changes from a high level to a low level. Suchan operation enables the noise signals from the pixels in the first rowto be held in the noise signal holding unit in the column circuit.

Next, at a timing T13, a φTX3 changes from a low level to a high level,and at a timing T14, the φTX3 changes from a high level to a low level.Such an operation enables signal charges for generating focal pointdetection signals for all pixels in the first row to be transferred fromthe second signal holding unit MEM2 to the input node of theamplification transistor SF.

At a timing T15, a PTS changes from a low level to a high level, and ata timing T16, the PTS changes from a high level to a low level. Such anoperation enables optical signals based on the signal charges forgenerating focal point detection signals generated at the firstphotoelectric conversion unit PD_A of pixels in the first row to be heldin the optical signal holding unit in the column circuit.

At timings T17 through T22, PHSEL_1 through PHSEL_3 are consecutivelychanged to an electroconductive state, which enables signals of eachpixel row to be consecutively output to the horizontal output lines.This period is called the horizontal scanning period (horizontallyenabled period). Such an operation enables signals based on the signalcharges for generating focal point detection signals generated at thefirst photoelectric conversion unit PD_A of pixels in the first row tobe read out to a device external to the imaging apparatus.

At a timing T23, a φSEL1 changes from a high level to a low level, and aφRES1 changes from a low level to a high level. Also, a φTX2_1 changesfrom a low level to a high level. In continuance, at a timing T24, theφSEL1 changes from a low level to a high level, and the φRES1 changesfrom high level to a low level. Also, the φTX2_1 changes from a highlevel to a low level. Such an operation enables the signals based on thesignal charges for generating focal point detection signals generated bythe second photoelectric conversion unit PD_B of the pixels in the firstrow to be held in the second signal holding unit MEM2.

At a timing T25, the PTN changes from a low level to a high level, andat a timing T26, the PTN changes from a high level to a low level. Suchan operation enables the noise signals from the pixels in the first rowto be held in the noise signal holding units in the column circuit.

At a timing T27, a φTX3 changes from a low level to a high level, and ata timing T28, the φTX3 changes from a high level to a low level. Such anoperation enables the signal charges for generating focal pointdetection signals from the multiple pixels in the first row to betransferred from the second signal holding unit MEM2 to the input nodeof the amplification transistor SF.

At a timing T29, the PTS changes from a low level to a high level, andat a timing T30, the PTS changes from a high level to a low level. Suchan operation enables the optical signals based on the signal charges forgenerating focal point detection signals generated by the secondphotoelectric conversion unit PD_B of the pixels in the first row to beheld in the optical signal holding unit in the circuit row.

At timings T31 through T36, PHSEL_1 through PHSEL_3 are consecutivelychanged to an electroconductive state, which enables signals of eachpixel row to be consecutively output to the horizontal output lines.This period is called the horizontal scanning period (horizontallyenabled period). Such an operation enables signals based on the signalcharges for generating focal point detection signals generated at thesecond photoelectric conversion unit PD_B of pixels in the first row tobe read out to a device external to the imaging apparatus.

At a timing T37, the φSEL1 changes from a high level to a low level. Thepixels in the first row change from a selectable state to anon-selectable state. In continuance, at timings T38 through T64, thesignals from the pixels in the second row are read out.

Next, at timings from T65, the signals from the pixels in the third roware read out. Similarly to those of the first row, the signals based onthe signal charges for generating focal point detection signalsgenerated at the first photoelectric conversion unit PD_A from thepixels in the third row are output.

Regarding the present example, the exposure period of the next framebegins during the read out period of the pixels in the third row. At atiming T66, the φOFD of all pixels on the imaging face change from ahigh level to a low level. Such an operation enables the signal chargesfor generating focal point detection signals generated from lightilluminated on the photoelectric conversion units PD_A and PD_B to beaccumulated in the photoelectric conversion units PD_A and PD_B.

Seventh Example

FIG. 31 illustrates an equivalent circuit diagram of the presentexample. The difference between the present example and the examplespreviously described is that the circuit configuration downstream of thesecond signal holding unit MEM2 includes multiple circuit blocks inparallel, and each of these includes multiple vertical signal linescorresponding to each circuit block. The portions that have the samefunctions as those in the previously described examples are denoted withthe same reference numerals, and thus their descriptions are omittedhere.

The present example includes multiple third charge transfer unitsdownstream of the second signal holding unit MEM2. Also, theamplification transistor, the reset transistor, and the selectiontransistor are disposed in each of the third charge transfer units. Theconfiguration enables control pulses to be supplied independently toenable independent operation of third charge transfer units TX3_A andTX3_B. As previously described, by provisioning multiple vertical signallines for example, operation may be controlled with a shared controlpulse to circuit elements which have the same function as that of thecircuits downstream of the third charge transfer units TX3_A and TX3_B.According to the present example, the speed of read out of signals maybe further improved as compared with the sixth Example or otherexamples.

FIG. 32 is a diagram illustrating an example of the control pulses inthe present example. All control pulses are at a high level and in anelectroconductive state. Further, the pulse PTS is a control pulse usedto hold signals in the photoelectric conversion unit disposed in thecolumn circuit. The pulse PTN is a control pulse used to hold signals inthe noise signal holding unit disposed in the column circuit. The pulsePHSEL is a control pulse output from the horizontal scanning circuit,and controls the read out of each row of signals held in the columncircuit to the horizontal signal lines. The driving pulses in FIG. 32may, for example, be used in a focal point detecting mode.

Until a timing T1, the φRES of all pixels on the imaging face are at ahigh level, and the reference voltage has been supplied to the gate ofthe amplification transistor. Other control pulses illustrated in FIG.32 are at a low level.

At the timing T1, the φTX1_A, φTX1_B, φTX2, φTX3_A, φTX3_B, and φOFD ofall pixels on the imaging face change from a low level to a high level.Next, at a timing T2, the φTX1_A, φTX1_B, φTX2, φTX3_A, φTX3_B, and φOFDof all pixels on the imaging face change from a high level to a lowlevel. Such an operation enables the charges in the first photoelectricconversion unit PD_A, the second photoelectric conversion unit PD_B, thefirst signal holding unit MEM1, and the second signal holding unit MEM2to be drained to the reset transistor drain via the OFD region or the FDregion. Also at the timing T2, the imaging exposure period of the nthframe begins. As illustrated in FIG. 32, the exposure period is the samefor the entire imaging face.

At a timing T3, the φTX1_A of all pixels in the first row on the imagingface change from a low level to a high level, and at a timing T4, theφTX1_A of all pixels in the first row on the imaging face change from ahigh level to a low level. Such an operation enables the signal chargesfor generating focal point detection signals in the first photoelectricconversion unit PD_A for all pixels on the imaging face to betransferred to the first signal holding unit MEM1.

At a timing T5, the φTX2 of all pixels on the imaging face change from alow level to a high level, and at a timing T6, the φTX2 of all pixels onthe imaging face change from a high level to a low level. Such anoperation enables the signal charges for generating focal pointdetection signals held in the first signal holding unit MEM1 to betransferred to the second signal holding unit MEM2 via the second chargetransfer unit TX2.

At a timing T7, the φTX1_B for all pixels on the imaging face changesfrom a low level to a high level, and at a timing T8, the φTX1_B for allpixels on the imaging face changes from a high level to a low level.Such an operation enables the signal charges for generating focal pointdetection signals in the second photoelectric conversion unit PD_B forall pixels on the imaging face to be transferred to the first signalholding MEM1.

At a timing T9, the φOFD of all pixels on the imaging face change from alow level to a high level, and the charges generated from lightilluminated on the photoelectric conversion units PD_A and PD_B aredrained to the OFD region.

At a timing T10, a φSEL_1 changes from a low level to a high level, andat the same time, a φRES_1 changes from a high level to a low level.Such an operation enables a state in which the noise signals of pixelsin the first row to be output to the vertical signal lines VOUT_A andVOUT_B.

At a timing T11, the PTN changes from a low level to a high level, andat a timing T12, the PTN changes from a high level to a low level. Suchan operation enables the noise signals from the pixels in the first rowto be held in the noise signal holding unit in the column circuit.

At a timing T13, a φTX3 changes from a low level to a high level, and ata timing T14, the φTX3 changes from a high level to a low level. Such anoperation enables signal charges for generating focal point detectionsignals for multiple pixels in the first row to be transferred from thesecond signal holding unit MEM2 to the input node of the amplificationtransistor SF.

At a timing T15, the φTX2 of all pixels on the imaging face changes froma low level to a high level, and at a timing T16, the φTX2 of all pixelson the imaging face changes from a high level to a low level. Such anoperation enables the signal charges for generating focal pointdetection signals generated at the second photoelectric conversion unitPD_B to be transferred from the first signal holding unit MEM1 to thesecond signal holding unit MEM2.

At a timing T17, the PTS changes from a low level to a high level.Further, a φTX3_B of all pixels on the imaging face change from a lowlevel to a high level. Such an operation enables the signal charges forgenerating focal point detection signals generated at the secondphotoelectric conversion unit PD_B to be transferred from the secondsignal holding unit MEM2 to the input node of the amplificationtransistor.

At a timing T18, the φTX3_B for all pixels on the imaging face changefrom a high level to a low level.

At a timing T19, the PTS changes from a high level to a low level.During the period for timings T17 through T19, the optical signals basedon signal charges for generating focal point detection signals generatedat the first photoelectric conversion unit PD_A and the secondphotoelectric conversion unit PD_B of pixels in the first row are heldin the photoelectric conversion unit in the column circuit.

At timings T20 through T25, PHSEL_1 through PHSEL_3 are consecutivelychanged to an electroconductive state, which enables signals of eachpixel row to be consecutively output to the horizontal output lines.This period is called the horizontal scanning period (horizontallyenabled period). Such an operation enables signals based on the signalcharges for generating focal point detection signals generated at thefirst photoelectric conversion unit PD_A and the second photoelectricconversion unit PD_B of pixels in the first row to be read out to adevice external to the imaging apparatus.

At a timing T26, a φSEL1 changes from a high level to a low level, and aφRES1 changes from a low level to a high level. The pixels in the firstrow change from a selectable state to a non-selectable state. Incontinuance, during the period for timings T27 through T44, the signalsfor pixels in the second row are read out. Also, at timings from T45,the signals for pixels in the third row are read out.

Regarding the present example, the exposure period of the next framebegins during the read out period of the pixels in the third row. At atiming T45, the φOFD of all pixels on the imaging face change from ahigh level to a low level. Such an operation enables the electronsgenerated from light illuminated on the photoelectric conversion unitsPD_A and PD_B to be accumulated in the photoelectric conversion unitsPD_A and PD_B.

Eighth Example

FIG. 33 is a top view of the imaging apparatus in the present example.Also, FIG. 34 is a diagram illustrating an equivalent circuit diagram ofthe first pixel of the imaging device in the present example. Thedifference between the present example and the examples previouslydescribed is a circuit element that is disposed from the firstphotoelectric conversion unit PD_A to the input node of theamplification transistor, and a circuit element that is disposed fromthe second photoelectric conversion unit PD_B to the input node of theamplification transistor. The first photoelectric conversion unit PD_Aand the second photoelectric conversion unit PD_B does not have to havethe same signal processing, and may be desirable to have differentprocessing depending on the situation. This would apply, for example, ifthe sensitivity of the first photoelectric conversion unit PD_A and thesecond photoelectric conversion unit PD_B are different. Also, if thesensitivity of the first photoelectric conversion unit PD_A and thesecond photoelectric conversion unit PD_B are not different, there arecases where different circuits are desirable due to restrictions on thedriving sequence or the like.

With reference to FIG. 34, the configuration related to the firstphotoelectric conversion unit PD_A has the first signal holding unitMEM1 disposed electrically between the output node of the firstphotoelectric conversion unit PD_A and the input node of theamplification transistor SF. In contrast, as an independentconfiguration that does not have a signal holding unit provisioned, onlythe second charge transfer unit TX2_B is disposed electrically betweenthe output node of the second photoelectric conversion unit PD_B and theinput node of the amplification transistor SF.

FIGS. 35 and 36 are diagrams illustrating specific driving pulses forthe imaging apparatus illustrated in FIG. 34. The mode illustrated inFIG. 35 is preferably used in a still image photography or similar mode.The mode illustrated in FIG. 36 is preferably used as a mode for focalpoint detection signals. Either set of control pulses are at a highlevel and in an electroconductive state. Further, the pulse PTS is acontrol pulse used to hold signals in the optical signal holding unitdisposed in the column circuit. The pulse PTN is a control pulsed usedto hold signals in the noise signal holding unit disposed in the columncircuit. The pulse PHSEL is a control pulse output from the horizontalscanning circuit, and controls the read out of each row of signals heldin the column circuit to the horizontal signal lines.

First, FIG. 35 will be described. Until a timing T1, the φRES of allpixels on the imaging face are at a high level, and the referencevoltage has been supplied to the gate of the amplification transistor.Other control pulses illustrated in FIG. 35 are at a low level.

At the timing T1, the φTX1, φTX2_A, φTX2_B, and φOFD of all pixels onthe imaging face change from a low level to a high level. Next, at atiming T2, the φTX1, φTX2_A, φTX2_B, and φOFD of all pixels on theimaging face change from a high level to a low level. Such an operationenables the charges in the first photoelectric conversion unit PD_A, thesecond photoelectric conversion unit PD_B, and the first signal holdingunit MEM1 to be drained to the reset transistor drain via the OFD regionor the FD region. Also at the timing T2, the imaging exposure period ofthe nth frame begins. As illustrated in FIG. 35, the exposure period isthe same for the entire imaging face.

At a timing T3, the φTX1 of all pixels in the first row on the imagingface change from a low level to a high level, and at a timing T4, theφTX1_A of all pixels in the first row on the imaging face change from ahigh level to a low level. Such an operation enables the signal chargesfor generating focal point detection signals in the first photoelectricconversion unit PD_A for all pixels on the imaging face to betransferred to the first signal holding MEM1.

At a timing T5, the φOFD of all pixels on the imaging face change from alow level to a high level, and the signal charges for generating focalpoint detection signals generated by light illuminated on thephotoelectric conversion units PD_A and PD_B are drained to the OFDregion.

At a timing T6, the φSEL_1 changes from a low level to a high level, andat the same time, the φRES_1 changes from a high level to a low level.Such an operation enables a state in which the noise signals of pixelsin the first row may be output to the vertical signal lines VOUT_A andVOUT_B.

At a timing T7, the PTN changes from a low level to a high level, and ata timing T8, the PTN changes from a high level to a low level. Such anoperation enables the noise signals from the pixels in the first row tobe held in the noise signal holding unit in the column circuit.

At a timing T9, the φTX2_A and φTX2_B of all pixels on the imaging facechange from a low level to a high level, and at a timing T10, the φTX2_Aand φTX2_B change from a high level to a low level. Such an operationenables signal charges for generating focal point detection signalsgenerated by the first photoelectric conversion unit PD_A and the signalcharges for generating focal point detection signals generated by thesecond photoelectric conversion unit PD_B, both of which are in multiplepixels in the first row, to be added at the gate of the amplificationtransistor SF. In other words, the signal charges for generating focalpoint detection signals generated by the first photoelectric conversionunit PD_A held at the first signal holding unit MEM1 and the signalcharges for generating focal point detection signals generated by thesecond photoelectric conversion unit PD_B are added at the gate of theamplification transistor SF.

At a timing T11, the PTS changes from a low level to a high level, andat a timing T12, the PTS changes from a high level to a low level. Suchan operation enables the optical signals obtained by adding the signalcharges for generating focal point detection signals generated at thefirst photoelectric conversion unit PD_A and the second photoelectricconversion unit PD_B, both of which are in the pixels in the first row,to be held in the optical signal holding unit in the column circuit.

At timings T13 through T18, the PHSEL_1 through PHSEL_3 areconsecutively changed to an electroconductive state, which enablessignals of each pixel row to be consecutively output to the horizontaloutput lines. This period is called the horizontal scanning period(horizontally enabled period). Such an operation enables signalsobtained by adding the signal charges for generating focal pointdetection signals generated at the first photoelectric conversion unitPD_A and the second photoelectric conversion unit PD_B, both of whichare in pixels in the first row, to be read out to a device external tothe imaging apparatus.

At a timing T19, the φSEL1 changes from a high level to a low level, andthe φRES1 changes from a low level to a high level. The pixels in thefirst row change from a selectable state to a non-selectable state. Incontinuance, during the period for timings T20 through T33, the signalsof pixels in the second row are read out. Also, at timings from T34, thesignals of pixels in the third row are read out.

Regarding the present example, the exposure period of the next framebegins during the read out period of the pixels in the third row. At atiming T34, the φOFD of all pixels on the imaging face change from ahigh level to a low level. Such an operation enables the signals chargesfor generating focal point detection signals generated from lightilluminated on the photoelectric conversion units PD_A and PD_B to beaccumulated in the photoelectric conversion units PD_A and PD_B.

Next, FIG. 36 will be described. Until a timing T1, the φRES of allpixels on the imaging face are at a high level, and the referencevoltage has been supplied to the gate of the amplification transistor.Other control pulses illustrated in FIG. 36 are at a low level.

At the timing T1, the φTX1, φTX2_A, φTX2_B, and φOFD of all pixels onthe imaging face change from a low level to a high level. Next, at atiming T2, the φTX1, φTX2_A, φTX2_B, and φOFD of all pixels on theimaging face change from a high level to a low level. Such an operationenables the charges in the first photoelectric conversion unit PD_A, thesecond photoelectric conversion unit PD_B, and the first signal holdingunit MEM1 to be drained to the reset transistor drain via the OFD regionor the FD region. Also at the timing T2, the imaging exposure period ofthe nth frame begins. As illustrated in FIG. 36, the exposure period isthe same for the entire imaging face.

At a timing T3, the φRES of all pixels on the imaging face change from ahigh level to a low level.

At a timing T4, the φTX1 and φTX2_B of all pixels on the imaging facechange from a low level to a high level, and at a timing T5, the φTX1and φTX2_B of all pixels on the imaging face change from a high level toa low level. Such an operation enables signal charges for generatingfocal point detection signals of the first photoelectric conversion unitPD_A in all pixels on the imaging face to be transferred to the firstsignal holding unit MEM1. Further, signal charges for generating focalpoint detection signals of the second photoelectric conversion unit PD_Bare transferred to the input node of the amplification transistor SF.

At a timing T6, the φOFD of all pixels on the imaging face change from alow level to a high level, and the signal charges generated by theillumination of light on the photoelectric conversion units PD_A andPD_B are drained to the OFD region.

At a timing T7, the φSEL_1 changes from a low level to a high level.Such an operation enables a state in which the signals based on thesignal charges for generating focal point detection signals generated bythe second photoelectric conversion unit PD_B in pixels in the first rowmay be read out to the vertical signal line VOUT.

At a timing T8, the PTS changes from a low level to a high level, and ata timing T9, the PTS changes from a high level to a low level. Such anoperation enables the optical signals based on the signal charges forgenerating focal point detection signals generated by the secondphotoelectric conversion unit PD_B in the pixels in the first row to beheld in the optical signal holding unit in the column circuit.

At timings T10 through T15, the PHSEL_1 through PHSEL_3 areconsecutively changed to an electroconductive state, which enablessignals of each pixel row to be consecutively output to the horizontaloutput lines. This period is called the horizontal scanning period(horizontally enabled period). Such an operation enables signals basedon the signal charges for generating focal point detection signalsgenerated at the second photoelectric conversion unit PD_B in pixels inthe first row to be read out to a device external to the imagingapparatus.

At a timing T16, the φSEL1 temporarily changes from a high level to alow level, and the φRES1 temporarily changes from a low level to a highlevel. At a timing T17, the φSEL1 changes from a low level to a highlevel, and the φRES1 temporarily changes from a high level to a lowlevel.

At a timing T18, a CTN changes from a low level to a high level, and ata timing T19, the CTN changes from a high level to a low level.

At a timing T20, the φTX2_A of all pixels on the imaging face changefrom a low level to a high level, and at a timing T21, the φTX2_A of allpixels on the imaging face change from a high level to a low level.

At a timing T22, the CTS changes from a low level to a high level, andat a timing T23, the CTS changes from a high level to a low level.

At timings T4 through T29, the PHSEL_1 through PHSEL_3 are consecutivelychanged to an electroconductive state, which enables signals of eachpixel row to be consecutively output to the horizontal output lines.This period is called the horizontal scanning period (horizontallyenabled period). Such an operation enables signals based on the signalcharges for generating focal point detection signals generated at thefirst photoelectric conversion unit PD_B in pixels in the first row tobe read out to a device external to the imaging apparatus.

At a timing T30, the φSEL1 changes from a high level to a low level, andthe φRES1 changes from a low level to a high level. Such an operationenables the pixels in the first row to change from a selectable state toa non-selectable state.

At timings T32 through T58, the signals of the pixels in the second roware read out in the same way. Also, at timings from T59, the signals ofthe pixels in the third row are read out. Regarding the present example,the optical signals and the noise signals from the first photoelectricconversion unit PD_A are output, and only the optical signals from thesecond photoelectric conversion unit PD_B are output.

Ninth Example

FIG. 37 is a diagram illustrating an equivalent circuit diagram of thefirst pixel in the present example. The difference between the presentexample and the eighth Example is the provisioning of independent pixeltransistors such as the amplification transistors corresponding to boththe first photoelectric conversion unit PD_A and the secondphotoelectric conversion unit PD_B. The portions that have the samefunctions as those in the previously described examples are denoted withthe same reference numerals, and thus their descriptions are omittedhere.

FIG. 38 is a diagram illustrating an example of the control pulsessupplied to the imaging region of the imaging apparatus in the presentexample. All control pulses are at a high level and in anelectroconductive state. Further, the pulses PTS_A and PTS_B are controlpulses used to hold signals in the optical signal holding unit disposedin the column circuit. The pulses PTN_A and PTN_B are control pulsesused to hold signals in the noise signal holding unit disposed in thecolumn circuit. The configuration of the present example has to enableindependent control of the first photoelectric conversion unit PD_A andthe second photoelectric conversion unit PD_B via a sample hold circuitsuch as a column circuit or similar.

The pulse PHSEL is a control pulse output from the horizontal scanningcircuit, and controls the read out of each row of signals held in thecolumn circuit to the horizontal signal lines.

Until a timing T1, the φRES of all pixels on the imaging face are at ahigh level, and the reference voltage has been supplied to the gate ofthe amplification transistor. Other control pulses illustrated in FIG.38 are at a low level.

At the timing T1, the φTX1, φTX2_A, φTX2_B, and φOFD of all pixels onthe imaging face change from a low level to a high level. Next, at atiming T2, the φTX1, φTX2_A, φTX2_B, and φOFD of all pixels on theimaging face change from a high level to a low level. Such an operationenables the charges in the first photoelectric conversion unit PD_A, thesecond photoelectric conversion unit PD_B, and the first signal holdingunit MEM1 to be drained to the reset transistor drain via the OFD regionor the FD region. Also at the timing T2, the imaging exposure period ofthe nth frame begins. As illustrated in FIG. 38, the exposure period isthe same for the entire imaging face.

At a timing T3, the φRES_B of all pixels on the imaging face change froma high level to a low level.

At a timing T4, the φTX1 and φTX2_B of all pixels on the imaging facechange from a low level to a high level, and at a timing T5, the φTX1and φTX2_B of all pixels on the imaging face change from a high level toa low level. Such an operation enables signal charges for generatingfocal point detection signals of the first photoelectric conversion unitPD_A of all pixels on the imaging face in all pixels in the first row tobe transferred to the first signal holding unit MEM1. Further, signalcharges for generating focal point detection signals of the secondphotoelectric conversion unit PD_B are transferred to the input node ofthe amplification transistor SF_B.

At a timing T6, the φOFD of all pixels on the imaging face change from alow level to a high level, and the signal charges generated by theillumination of light on the photoelectric conversion units PD_A andPD_B are drained to the OFD region.

At a timing T7, the φSEL_1 changes from a low level to a high level.Such an operation enables a state in which the signals of pixels in thefirst row may be read out to the vertical signal lines VOUT_A andVOUT_B. Further, the φRES_A of all pixels on the imaging face changefrom a high level to a low level.

At a timing T8, the PTS_A and PTS_B change from a low level to a highlevel, and at a timing T9, the PTN_A and PTS_B change from a high levelto a low level. Such an operation enables the noise signals generated onthe electrical pathway of the first photoelectric conversion unit PD_Ain the first row to be held in the noise signal holding unit in thecolumn circuit. Further, the optical signals based on the signal chargesfor generating focal point detection signals generated by the secondphotoelectric conversion unit PD_B of pixels in the first row to be heldin the optical signal holding unit in the column circuit.

At a timing T10, the φRES_B_1 and φTX2_A_1 change from a low level to ahigh level. Such an operation enables the reference voltage to besupplied to the voltage of the input node of the amplificationtransistor SF_B. Further, the signals held in the first signal holdingunit MEM1 of pixels in the first row are transferred to the input nodeof the amplification transistor SF_A. Then, at a timing T11, theφRES_B_1 and φTX2_A_1 change from a high level to a low level.

At a timing T12, the PTS_A and PTN_B change from a low level to a highlevel, and at a timing T13, the PTS_A and PTN_B change from a high levelto a low level. Such an operation enables the noise signals generated onthe electrical pathway of the second photoelectric conversion unit PD_Ain the first row to be held in the noise signal holding unit in thecolumn circuit. Further, the optical signals based on the signal chargesfor generating focal point detection signals generated by the firstphotoelectric conversion unit PD_B of pixels in the first row to be heldin the optical signal holding unit in the column circuit.

At timings T14 through T19, the PHSEL_1 through PHSEL_3 areconsecutively changed to an electroconductive state, which enablessignals of each pixel row to be consecutively output to the horizontaloutput lines. This period is called the horizontal scanning period(horizontally enabled period). Such an operation enables the opticalsignal and the noise signals of pixels in the first row to be read outto a device external to the imaging apparatus.

At a timing T20, the φSEL1 changes from a high level to a low level, andthe φRES_A_1 and φRES_B_1 change from a low level to a high level. Suchan operation enables the first row to change from a selectable state toa non-selectable state.

From a timing T20 on, the signals of the pixels in the second row areread out in the same way.

Focal Point Detection Mechanism

The focal point detection regarding the imaging face of the imagingapparatus in the previously described examples will be described here.Specifically, one example of the phase contrast detection will bedescribed where the focal point detection is performed during imaging onthe imaging face.

This will be described with reference to FIGS. 39 and 40. FIG. 39 is aconceptual diagram illustrating light beams from an exit pupil of anphotography lens 3900 illuminated on an imaging apparatus 3901. MLrepresents a microlens, CF represents a color filter, and thephotoelectric conversion unit PD1 and PD2 represent multiplephotoelectric conversion units on which light condensed from onemicrolens is illuminated. Reference numeral 3902 denotes the exit pupilof the photography lens. Here, one pixel includes one microlens ML, andthe focus of light beams condensed from the exit pupil 3902 isrepresented by an optical axis 3903. Light emitted from the exit pupilis input to the imaging apparatus 3901, primarily on the optical axis3903. Light beams on the outer rings of light that pass through apartial region 3904 of the exit pupil are denoted with 3906 and 3907.Light beams on the outer rings of light that passes through a partialregion 3905 of the exit pupil 3902 are denoted by 3908 and 3909. As canbe inferred from FIG. 39, with the optical axis 3903 as a boundary, theupper portion of the light beam that leaves from the exit pupil 3902 isilluminated onto the PD1, and the lower portion of the light beam isilluminated onto the PD2. That is to say, the PD1 and the PD2 eachreceive light from different regions of the exit pupil of thephotography lens.

This property is used to perform the detection of phase contrasts. Whenlooking at the imaging region from the top surface in regard to theregion within the pixel, the light condensed by the single microlens isilluminated onto multiple photoelectric conversion units, and so thedata obtained from one PD is represented as the first line, and the dataobtained from the other PD is represented as the second line. Thus, theobtaining of the correlation data between the two lines enables thedetection of phases.

Regarding FIG. 39, let us say for example the light condensed by thesingle microlens is illuminated onto multiple photoelectric conversionunits, and so the data obtained from the PD disposed in the lower regionis represented as the first line, and the data obtained from the PDdisposed in the upper region is represented as the second line. In thiscase, PD1 outputs one pixel worth of the data from the first line, andthe PD2 outputs one pixel worth of the data from the second line. FIGS.40A and 40B illustrate the line data at a time when a point light sourceforms an image. FIG. 40A illustrates data of the first line and secondline when in focus. The horizontal axis represents the pixel position,and the vertical axis represents the output. The first line and thesecond line overlap when in focus. FIG. 40B illustrates the case whenthis is out of focus. In this case, the first line and second line havephase difference, and pixel positions are shifted. By calculating ashift amount 1001, how far out of focus the image is from when in focusis determined. Such a method enables an image to be set into focus bydetection the phase and driving the lens.

Next, image data generation from these pixel arrays will be described.As previously described, the focus may be detected by independentlyreading out signals from the PD1 and the PD2 from the imaging apparatus3901, and then performing a calculation to detect the phase contrast.Also, the photographed image may be generated by adding the signals fromthe PD where light condensed from one microlens has been illuminated.

Although FIG. 39 describes pixels near the center of the imaging device,there is a significant difference in the amount of light actuallyilluminated between PDs of pixels on the outer right of the imagingdevice, and for this reason, focal point detection pixels with a higherprecision may be disposed in the outer portion than those disposed inthe center of the imaging region.

Application to Imaging System

FIG. 41 illustrates an example of an imaging system that may employ theimaging apparatus of the previously described embodiments. In FIG. 41, alens unit 4101 performs zoom control, focus control, and aperturecontrol by a lens driving apparatus 4102 at lens unit where an imagingapparatus 4105 forms the image from the optical image of the object. Ashutter 4103 controls a mechanical shutter by a shutter drivingapparatus 4104. A global electron shutter is enabled by using theconfiguration of the present technology, and so the mechanical shutterdoes not have to be used; however, it is preferable to have an operationmode that is switchable depending on usage.

Reference numeral 4105 denotes an imaging apparatus for handling theobject of the image to be formed by the lens unit 4101 as image signals,and reference numeral 4106 denotes an imaging signal processing circuitthat performs various corrections on the imaging signals output from theimaging apparatus 4105, compression of the data, and other functions.Reference numeral 4107 denotes a timing generating circuit includes adriving method to output each type of timing signal to the imagingapparatus 4105 and the imaging signal processing circuit 4106. Referencenumeral 4109 denotes a control circuit that controls each type ofcalculation and the entire imaging apparatus, reference numeral 4108denotes a memory that temporarily stores the image data, and referencenumeral 4110 denotes an interface that performs the recording to andreading out from a recording medium. Reference numeral 4111 denotes aremovable recording medium such as semiconductor memory that performsthe recording and the reading out of image data, and reference numeral4112 denotes a display unit that displays each type of information andthe photographed image.

Next, the operation of a digital camera using the previously describedconfiguration during photography will be described. When the main poweris turned on, the control system power is turned on, and further theimaging system circuit such as the imaging signal processing circuit1106 is turned on.

Then, when the release button (not illustrated) is pressed, a rangingcalculation is performed from the data from the imaging apparatus 4105,a calculation of the distance to the object based on the ranging resultis performed at the control circuit 4109. Afterwards, the lens unit isdriven by the lens driving apparatus 4102, and then the state of focusis determined, and if the image is determined to still not be in focus,the lens unit is driven again, and to complete the focus operation.Instead of being obtained from data from the imaging apparatus, theranging calculation may be performed by a dedicated ranging apparatus(not illustrated).

The photography operation then begins after the focus has beenconfirmed. When the photography operation ends, the image signals outputfrom the imaging apparatus 4105 are image processes by the photographysignal processing circuit 4106, and written to memory by the controlcircuit 4109. Sort processing, additive processing, and some selectedprocessing is performed at the photography signal processing circuit.The data accumulated in the memory 4108 is stored in the removablerecording medium 4111 such as semiconductor memory through the recordingmedium control interface unit 4110 by control from the control circuit4109.

Also, the images may be input directly to a computer or similar throughan external interface (not illustrated) and processed further there.

While the present invention has been described with reference toexemplary embodiments, it is to be understood that the invention is notlimited to the disclosed exemplary embodiments. The scope of thefollowing claims is to be accorded the broadest interpretation so as toencompass all such modifications and equivalent structures andfunctions.

What is claimed is:
 1. An imaging apparatus comprising: a plurality ofpixels each including a photoelectric conversion unit, and anamplification element to amplify signals based on signal chargesgenerated by the photoelectric conversion unit, in which the pluralityof pixels output signals for performing a phase contrast detection typeof focal point detection; and a signal holding unit in an electricalpathway between an output node of the photoelectric conversion unit andan input node of the amplification element, in which signals forperforming the phase contrast detection type of focal point detectionare held.